Merge tag 'u-boot-imx-20190426' of git://git.denx.de/u-boot-imx
[oweals/u-boot.git] / arch / arm / dts / vf-colibri.dtsi
1 // SPDX-License-Identifier: GPL-2.0+ OR X11
2 /*
3  * Copyright 2014-2019 Toradex AG
4  */
5
6 /dts-v1/;
7 #include "vf.dtsi"
8 #include "vf610-pinfunc.h"
9
10 / {
11         chosen {
12                 stdout-path = &uart0;
13         };
14
15         aliases {
16                 usb0 = &ehci0; /* required for ums */
17         };
18
19         reg_usbh_vbus: regulator-usbh-vbus {
20                 compatible = "regulator-fixed";
21                 pinctrl-names = "default";
22                 pinctrl-0 = <&pinctrl_usbh1_reg>;
23                 regulator-name = "VCC_USB[1-4]";
24                 regulator-min-microvolt = <5000000>;
25                 regulator-max-microvolt = <5000000>;
26                 gpio = <&gpio2 19 GPIO_ACTIVE_LOW>; /* USBH_PEN */
27         };
28 };
29
30 &dspi1 {
31         bus-num = <1>;
32         pinctrl-names = "default";
33         pinctrl-0 = <&pinctrl_dspi1>;
34         status = "okay";
35
36         spi_cmd: sspi@0 {
37                 reg = <0>;
38                 spi-max-frequency = <50000000>;
39         };
40 };
41
42 &ehci0 {
43         dr_mode = "otg";
44         fsl,cdet-gpio = <&gpio3 6 GPIO_ACTIVE_HIGH>;
45         status = "okay";
46 };
47
48 &ehci1 {
49         dr_mode = "host";
50         status = "okay";
51         vbus-supply = <&reg_usbh_vbus>;
52 };
53
54 &esdhc1 {
55         bus-width = <4>;
56         cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
57         disable-wp;
58         pinctrl-names = "default";
59         pinctrl-0 = <&pinctrl_esdhc1>;
60         status = "okay";
61 };
62
63 /* Ethernet */
64 &fec1 {
65         phy-mode = "rmii";
66         phy-handle = <&ethphy1>;
67         pinctrl-names = "default";
68         pinctrl-0 = <&pinctrl_fec1>;
69         status = "okay";
70
71         mdio {
72                 #address-cells = <1>;
73                 #size-cells = <0>;
74
75                 ethphy1: ethernet-phy@1 {
76                         compatible = "ethernet-phy-ieee802.3-c22";
77                         max-speed = <100>;
78                         reg = <1>;
79                 };
80         };
81 };
82
83 &i2c0 {
84         clock-frequency = <400000>;
85         pinctrl-names = "default";
86         pinctrl-0 = <&pinctrl_i2c0>;
87         status = "okay";
88
89         /* M41T0M6 real time clock on carrier board */
90         rtc: m41t0m6@68 {
91                 compatible = "st,m41t0";
92                 reg = <0x68>;
93         };
94 };
95
96 &iomuxc {
97         pinctrl-names = "default";
98         pinctrl-0 = <&pinctrl_ddr>;
99
100         pinctrl_ddr: ddrgrp {
101                 fsl,pins = <
102                         VF610_PAD_DDR_A15__DDR_A_15             0x180
103                         VF610_PAD_DDR_A14__DDR_A_14             0x180
104                         VF610_PAD_DDR_A13__DDR_A_13             0x180
105                         VF610_PAD_DDR_A12__DDR_A_12             0x180
106                         VF610_PAD_DDR_A11__DDR_A_11             0x180
107                         VF610_PAD_DDR_A10__DDR_A_10             0x180
108                         VF610_PAD_DDR_A9__DDR_A_9               0x180
109                         VF610_PAD_DDR_A8__DDR_A_8               0x180
110                         VF610_PAD_DDR_A7__DDR_A_7               0x180
111                         VF610_PAD_DDR_A6__DDR_A_6               0x180
112                         VF610_PAD_DDR_A5__DDR_A_5               0x180
113                         VF610_PAD_DDR_A4__DDR_A_4               0x180
114                         VF610_PAD_DDR_A3__DDR_A_3               0x180
115                         VF610_PAD_DDR_A2__DDR_A_2               0x180
116                         VF610_PAD_DDR_A1__DDR_A_1               0x180
117                         VF610_PAD_DDR_A0__DDR_A_0               0x180
118                         VF610_PAD_DDR_BA2__DDR_BA_2             0x180
119                         VF610_PAD_DDR_BA1__DDR_BA_1             0x180
120                         VF610_PAD_DDR_BA0__DDR_BA_0             0x180
121                         VF610_PAD_DDR_CAS__DDR_CAS_B            0x180
122                         VF610_PAD_DDR_CKE__DDR_CKE_0            0x180
123                         VF610_PAD_DDR_CLK__DDR_CLK_0            0x180
124                         VF610_PAD_DDR_CS__DDR_CS_B_0            0x180
125                         VF610_PAD_DDR_D15__DDR_D_15             0x10180
126                         VF610_PAD_DDR_D14__DDR_D_14             0x10180
127                         VF610_PAD_DDR_D13__DDR_D_13             0x10180
128                         VF610_PAD_DDR_D12__DDR_D_12             0x10180
129                         VF610_PAD_DDR_D11__DDR_D_11             0x10180
130                         VF610_PAD_DDR_D10__DDR_D_10             0x10180
131                         VF610_PAD_DDR_D9__DDR_D_9               0x10180
132                         VF610_PAD_DDR_D8__DDR_D_8               0x10180
133                         VF610_PAD_DDR_D7__DDR_D_7               0x10180
134                         VF610_PAD_DDR_D6__DDR_D_6               0x10180
135                         VF610_PAD_DDR_D5__DDR_D_5               0x10180
136                         VF610_PAD_DDR_D4__DDR_D_4               0x10180
137                         VF610_PAD_DDR_D3__DDR_D_3               0x10180
138                         VF610_PAD_DDR_D2__DDR_D_2               0x10180
139                         VF610_PAD_DDR_D1__DDR_D_1               0x10180
140                         VF610_PAD_DDR_D0__DDR_D_0               0x10180
141                         VF610_PAD_DDR_DQM1__DDR_DQM_1           0x10180
142                         VF610_PAD_DDR_DQM0__DDR_DQM_0           0x10180
143                         VF610_PAD_DDR_DQS1__DDR_DQS_1           0x10180
144                         VF610_PAD_DDR_DQS0__DDR_DQS_0           0x10180
145                         VF610_PAD_DDR_RAS__DDR_RAS_B            0x180
146                         VF610_PAD_DDR_WE__DDR_WE_B              0x180
147                         VF610_PAD_DDR_ODT1__DDR_ODT_0           0x180
148                         VF610_PAD_DDR_ODT0__DDR_ODT_1           0x180
149                         VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1    0x180
150                         VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2    0x180
151                         VF610_PAD_DDR_RESETB                    0x180
152                 >;
153         };
154
155         pinctrl_dspi1: dspi1grp {
156                 fsl,pins = <
157                         VF610_PAD_PTD5__DSPI1_CS0               0x33e2
158                         VF610_PAD_PTD6__DSPI1_SIN               0x33e1
159                         VF610_PAD_PTD7__DSPI1_SOUT              0x33e2
160                         VF610_PAD_PTD8__DSPI1_SCK               0x33e2
161                 >;
162         };
163
164         pinctrl_esdhc1: esdhc1grp {
165                 fsl,pins = <
166                         VF610_PAD_PTA24__ESDHC1_CLK             0x31ef
167                         VF610_PAD_PTA25__ESDHC1_CMD             0x31ef
168                         VF610_PAD_PTA26__ESDHC1_DAT0            0x31ef
169                         VF610_PAD_PTA27__ESDHC1_DAT1            0x31ef
170                         VF610_PAD_PTA28__ESDHC1_DATA2           0x31ef
171                         VF610_PAD_PTA29__ESDHC1_DAT3            0x31ef
172                         VF610_PAD_PTB20__GPIO_42                0x219d
173                 >;
174         };
175
176         pinctrl_fec1: fec1grp {
177                 fsl,pins = <
178                         VF610_PAD_PTA6__RMII_CLKOUT             0x30df
179                         VF610_PAD_PTC9__ENET_RMII1_MDC          0x30df
180                         VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30df
181                         VF610_PAD_PTC11__ENET_RMII1_CRS         0x30df
182                         VF610_PAD_PTC12__ENET_RMII1_RXD1        0x30df
183                         VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30df
184                         VF610_PAD_PTC14__ENET_RMII1_RXER        0x30df
185                         VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30df
186                         VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30df
187                         VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30df
188                 >;
189         };
190
191         pinctrl_i2c0: i2c0grp {
192                 fsl,pins = <
193                         VF610_PAD_PTB14__I2C0_SCL               0x37ff
194                         VF610_PAD_PTB15__I2C0_SDA               0x37ff
195                 >;
196         };
197
198         pinctrl_nfc: nfcgrp {
199                 fsl,pins = <
200                         VF610_PAD_PTD23__NF_IO7                 0x28df
201                         VF610_PAD_PTD22__NF_IO6                 0x28df
202                         VF610_PAD_PTD21__NF_IO5                 0x28df
203                         VF610_PAD_PTD20__NF_IO4                 0x28df
204                         VF610_PAD_PTD19__NF_IO3                 0x28df
205                         VF610_PAD_PTD18__NF_IO2                 0x28df
206                         VF610_PAD_PTD17__NF_IO1                 0x28df
207                         VF610_PAD_PTD16__NF_IO0                 0x28df
208                         VF610_PAD_PTB24__NF_WE_B                0x28c2
209                         VF610_PAD_PTB25__NF_CE0_B               0x28c2
210                         VF610_PAD_PTB27__NF_RE_B                0x28c2
211                         VF610_PAD_PTC26__NF_RB_B                0x283d
212                         VF610_PAD_PTC27__NF_ALE                 0x28c2
213                         VF610_PAD_PTC28__NF_CLE                 0x28c2
214                 >;
215         };
216
217         pinctrl_uart0: uart0grp {
218                 fsl,pins = <
219                         VF610_PAD_PTB10__UART0_TX               0x11af
220                         VF610_PAD_PTB11__UART0_RX               0x11af
221                         VF610_PAD_PTB12__UART0_RTS              0x11af
222                         VF610_PAD_PTB13__UART0_CTS              0x11af
223                 >;
224         };
225
226         pinctrl_usbh1_reg: gpio_usb_vbus {
227                 fsl,pins = <
228                         VF610_PAD_PTD4__GPIO_83                 0x22ed
229                 >;
230         };
231 };
232
233 &nfc {
234         pinctrl-names = "default";
235         pinctrl-0 = <&pinctrl_nfc>;
236         status = "okay";
237 };
238
239 &uart0 {
240         pinctrl-names = "default";
241         pinctrl-0 = <&pinctrl_uart0>;
242         status = "okay";
243 };