arch/arm/dts/uniphier-sld8.dtsi

   1 /*
   2  * Device Tree Source for UniPhier sLD8 SoC
   3  *
   4  * Copyright (C) 2015-2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   8  */
   9
  10 #include <dt-bindings/gpio/uniphier-gpio.h>
  11
  12 / {
  13         compatible = "socionext,uniphier-sld8";
  14         #address-cells = <1>;
  15         #size-cells = <1>;
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20
  21                 cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a9";
  24                         reg = <0>;
  25                         enable-method = "psci";
  26                         next-level-cache = <&l2>;
  27                 };
  28         };
  29
  30         psci {
  31                 compatible = "arm,psci-0.2";
  32                 method = "smc";
  33         };
  34
  35         clocks {
  36                 refclk: ref {
  37                         compatible = "fixed-clock";
  38                         #clock-cells = <0>;
  39                         clock-frequency = <25000000>;
  40                 };
  41
  42                 arm_timer_clk: arm-timer {
  43                         #clock-cells = <0>;
  44                         compatible = "fixed-clock";
  45                         clock-frequency = <50000000>;
  46                 };
  47         };
  48
  49         soc {
  50                 compatible = "simple-bus";
  51                 #address-cells = <1>;
  52                 #size-cells = <1>;
  53                 ranges;
  54                 interrupt-parent = <&intc>;
  55
  56                 l2: l2-cache@500c0000 {
  57                         compatible = "socionext,uniphier-system-cache";
  58                         reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
  59                               <0x506c0000 0x400>;
  60                         interrupts = <0 174 4>, <0 175 4>;
  61                         cache-unified;
  62                         cache-size = <(256 * 1024)>;
  63                         cache-sets = <256>;
  64                         cache-line-size = <128>;
  65                         cache-level = <2>;
  66                 };
  67
  68                 serial0: serial@54006800 {
  69                         compatible = "socionext,uniphier-uart";
  70                         status = "disabled";
  71                         reg = <0x54006800 0x40>;
  72                         interrupts = <0 33 4>;
  73                         pinctrl-names = "default";
  74                         pinctrl-0 = <&pinctrl_uart0>;
  75                         clocks = <&peri_clk 0>;
  76                         clock-frequency = <80000000>;
  77                         resets = <&peri_rst 0>;
  78                 };
  79
  80                 serial1: serial@54006900 {
  81                         compatible = "socionext,uniphier-uart";
  82                         status = "disabled";
  83                         reg = <0x54006900 0x40>;
  84                         interrupts = <0 35 4>;
  85                         pinctrl-names = "default";
  86                         pinctrl-0 = <&pinctrl_uart1>;
  87                         clocks = <&peri_clk 1>;
  88                         clock-frequency = <80000000>;
  89                         resets = <&peri_rst 1>;
  90                 };
  91
  92                 serial2: serial@54006a00 {
  93                         compatible = "socionext,uniphier-uart";
  94                         status = "disabled";
  95                         reg = <0x54006a00 0x40>;
  96                         interrupts = <0 37 4>;
  97                         pinctrl-names = "default";
  98                         pinctrl-0 = <&pinctrl_uart2>;
  99                         clocks = <&peri_clk 2>;
 100                         clock-frequency = <80000000>;
 101                         resets = <&peri_rst 2>;
 102                 };
 103
 104                 serial3: serial@54006b00 {
 105                         compatible = "socionext,uniphier-uart";
 106                         status = "disabled";
 107                         reg = <0x54006b00 0x40>;
 108                         interrupts = <0 29 4>;
 109                         pinctrl-names = "default";
 110                         pinctrl-0 = <&pinctrl_uart3>;
 111                         clocks = <&peri_clk 3>;
 112                         clock-frequency = <80000000>;
 113                         resets = <&peri_rst 3>;
 114                 };
 115
 116                 gpio: gpio@55000000 {
 117                         compatible = "socionext,uniphier-gpio";
 118                         reg = <0x55000000 0x200>;
 119                         interrupt-parent = <&aidet>;
 120                         interrupt-controller;
 121                         #interrupt-cells = <2>;
 122                         gpio-controller;
 123                         #gpio-cells = <2>;
 124                         gpio-ranges = <&pinctrl 0 0 0>,
 125                                       <&pinctrl 104 0 0>,
 126                                       <&pinctrl 112 0 0>;
 127                         gpio-ranges-group-names = "gpio_range0",
 128                                                   "gpio_range1",
 129                                                   "gpio_range2";
 130                         ngpios = <136>;
 131                         socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
 132                 };
 133
 134                 i2c0: i2c@58400000 {
 135                         compatible = "socionext,uniphier-i2c";
 136                         status = "disabled";
 137                         reg = <0x58400000 0x40>;
 138                         #address-cells = <1>;
 139                         #size-cells = <0>;
 140                         interrupts = <0 41 1>;
 141                         pinctrl-names = "default";
 142                         pinctrl-0 = <&pinctrl_i2c0>;
 143                         clocks = <&peri_clk 4>;
 144                         resets = <&peri_rst 4>;
 145                         clock-frequency = <100000>;
 146                 };
 147
 148                 i2c1: i2c@58480000 {
 149                         compatible = "socionext,uniphier-i2c";
 150                         status = "disabled";
 151                         reg = <0x58480000 0x40>;
 152                         #address-cells = <1>;
 153                         #size-cells = <0>;
 154                         interrupts = <0 42 1>;
 155                         pinctrl-names = "default";
 156                         pinctrl-0 = <&pinctrl_i2c1>;
 157                         clocks = <&peri_clk 5>;
 158                         resets = <&peri_rst 5>;
 159                         clock-frequency = <100000>;
 160                 };
 161
 162                 /* chip-internal connection for DMD */
 163                 i2c2: i2c@58500000 {
 164                         compatible = "socionext,uniphier-i2c";
 165                         reg = <0x58500000 0x40>;
 166                         #address-cells = <1>;
 167                         #size-cells = <0>;
 168                         interrupts = <0 43 1>;
 169                         pinctrl-names = "default";
 170                         pinctrl-0 = <&pinctrl_i2c2>;
 171                         clocks = <&peri_clk 6>;
 172                         resets = <&peri_rst 6>;
 173                         clock-frequency = <400000>;
 174                 };
 175
 176                 i2c3: i2c@58580000 {
 177                         compatible = "socionext,uniphier-i2c";
 178                         status = "disabled";
 179                         reg = <0x58580000 0x40>;
 180                         #address-cells = <1>;
 181                         #size-cells = <0>;
 182                         interrupts = <0 44 1>;
 183                         pinctrl-names = "default";
 184                         pinctrl-0 = <&pinctrl_i2c3>;
 185                         clocks = <&peri_clk 7>;
 186                         resets = <&peri_rst 7>;
 187                         clock-frequency = <100000>;
 188                 };
 189
 190                 system_bus: system-bus@58c00000 {
 191                         compatible = "socionext,uniphier-system-bus";
 192                         status = "disabled";
 193                         reg = <0x58c00000 0x400>;
 194                         #address-cells = <2>;
 195                         #size-cells = <1>;
 196                         pinctrl-names = "default";
 197                         pinctrl-0 = <&pinctrl_system_bus>;
 198                 };
 199
 200                 smpctrl@59801000 {
 201                         compatible = "socionext,uniphier-smpctrl";
 202                         reg = <0x59801000 0x400>;
 203                 };
 204
 205                 mioctrl@59810000 {
 206                         compatible = "socionext,uniphier-sld8-mioctrl",
 207                                      "simple-mfd", "syscon";
 208                         reg = <0x59810000 0x800>;
 209
 210                         mio_clk: clock {
 211                                 compatible = "socionext,uniphier-sld8-mio-clock";
 212                                 #clock-cells = <1>;
 213                         };
 214
 215                         mio_rst: reset {
 216                                 compatible = "socionext,uniphier-sld8-mio-reset";
 217                                 #reset-cells = <1>;
 218                         };
 219                 };
 220
 221                 perictrl@59820000 {
 222                         compatible = "socionext,uniphier-sld8-perictrl",
 223                                      "simple-mfd", "syscon";
 224                         reg = <0x59820000 0x200>;
 225
 226                         peri_clk: clock {
 227                                 compatible = "socionext,uniphier-sld8-peri-clock";
 228                                 #clock-cells = <1>;
 229                         };
 230
 231                         peri_rst: reset {
 232                                 compatible = "socionext,uniphier-sld8-peri-reset";
 233                                 #reset-cells = <1>;
 234                         };
 235                 };
 236
 237                 sd: sdhc@5a400000 {
 238                         compatible = "socionext,uniphier-sdhc";
 239                         status = "disabled";
 240                         reg = <0x5a400000 0x200>;
 241                         interrupts = <0 76 4>;
 242                         pinctrl-names = "default", "1.8v";
 243                         pinctrl-0 = <&pinctrl_sd>;
 244                         pinctrl-1 = <&pinctrl_sd_1v8>;
 245                         clocks = <&mio_clk 0>;
 246                         reset-names = "host", "bridge";
 247                         resets = <&mio_rst 0>, <&mio_rst 3>;
 248                         bus-width = <4>;
 249                         cap-sd-highspeed;
 250                         sd-uhs-sdr12;
 251                         sd-uhs-sdr25;
 252                         sd-uhs-sdr50;
 253                 };
 254
 255                 emmc: sdhc@5a500000 {
 256                         compatible = "socionext,uniphier-sdhc";
 257                         status = "disabled";
 258                         reg = <0x5a500000 0x200>;
 259                         interrupts = <0 78 4>;
 260                         pinctrl-names = "default", "1.8v";
 261                         pinctrl-0 = <&pinctrl_emmc>;
 262                         pinctrl-1 = <&pinctrl_emmc_1v8>;
 263                         clocks = <&mio_clk 1>;
 264                         reset-names = "host", "bridge";
 265                         resets = <&mio_rst 1>, <&mio_rst 4>;
 266                         bus-width = <8>;
 267                         non-removable;
 268                         cap-mmc-highspeed;
 269                         cap-mmc-hw-reset;
 270                 };
 271
 272                 usb0: usb@5a800100 {
 273                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 274                         status = "disabled";
 275                         reg = <0x5a800100 0x100>;
 276                         interrupts = <0 80 4>;
 277                         pinctrl-names = "default";
 278                         pinctrl-0 = <&pinctrl_usb0>;
 279                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
 280                                  <&mio_clk 12>;
 281                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 282                                  <&mio_rst 12>;
 283                 };
 284
 285                 usb1: usb@5a810100 {
 286                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 287                         status = "disabled";
 288                         reg = <0x5a810100 0x100>;
 289                         interrupts = <0 81 4>;
 290                         pinctrl-names = "default";
 291                         pinctrl-0 = <&pinctrl_usb1>;
 292                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
 293                                  <&mio_clk 13>;
 294                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 295                                  <&mio_rst 13>;
 296                 };
 297
 298                 usb2: usb@5a820100 {
 299                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 300                         status = "disabled";
 301                         reg = <0x5a820100 0x100>;
 302                         interrupts = <0 82 4>;
 303                         pinctrl-names = "default";
 304                         pinctrl-0 = <&pinctrl_usb2>;
 305                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
 306                                  <&mio_clk 14>;
 307                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
 308                                  <&mio_rst 14>;
 309                 };
 310
 311                 soc-glue@5f800000 {
 312                         compatible = "socionext,uniphier-sld8-soc-glue",
 313                                      "simple-mfd", "syscon";
 314                         reg = <0x5f800000 0x2000>;
 315
 316                         pinctrl: pinctrl {
 317                                 compatible = "socionext,uniphier-sld8-pinctrl";
 318                         };
 319                 };
 320
 321                 timer@60000200 {
 322                         compatible = "arm,cortex-a9-global-timer";
 323                         reg = <0x60000200 0x20>;
 324                         interrupts = <1 11 0x104>;
 325                         clocks = <&arm_timer_clk>;
 326                 };
 327
 328                 timer@60000600 {
 329                         compatible = "arm,cortex-a9-twd-timer";
 330                         reg = <0x60000600 0x20>;
 331                         interrupts = <1 13 0x104>;
 332                         clocks = <&arm_timer_clk>;
 333                 };
 334
 335                 intc: interrupt-controller@60001000 {
 336                         compatible = "arm,cortex-a9-gic";
 337                         reg = <0x60001000 0x1000>,
 338                               <0x60000100 0x100>;
 339                         #interrupt-cells = <3>;
 340                         interrupt-controller;
 341                 };
 342
 343                 aidet: aidet@61830000 {
 344                         compatible = "socionext,uniphier-sld8-aidet";
 345                         reg = <0x61830000 0x200>;
 346                         interrupt-controller;
 347                         #interrupt-cells = <2>;
 348                 };
 349
 350                 sysctrl@61840000 {
 351                         compatible = "socionext,uniphier-sld8-sysctrl",
 352                                      "simple-mfd", "syscon";
 353                         reg = <0x61840000 0x10000>;
 354
 355                         sys_clk: clock {
 356                                 compatible = "socionext,uniphier-sld8-clock";
 357                                 #clock-cells = <1>;
 358                         };
 359
 360                         sys_rst: reset {
 361                                 compatible = "socionext,uniphier-sld8-reset";
 362                                 #reset-cells = <1>;
 363                         };
 364                 };
 365
 366                 nand: nand@68000000 {
 367                         compatible = "socionext,uniphier-denali-nand-v5a";
 368                         status = "disabled";
 369                         reg-names = "nand_data", "denali_reg";
 370                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 371                         interrupts = <0 65 4>;
 372                         pinctrl-names = "default";
 373                         pinctrl-0 = <&pinctrl_nand2cs>;
 374                         clocks = <&sys_clk 2>;
 375                         resets = <&sys_rst 2>;
 376                 };
 377         };
 378 };
 379
 380 #include "uniphier-pinctrl.dtsi"