2 * Device Tree Source for UniPhier sLD8 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
47 compatible = "socionext,uniphier-sld8";
57 compatible = "arm,cortex-a9";
59 enable-method = "psci";
60 next-level-cache = <&l2>;
65 compatible = "arm,psci-0.2";
71 compatible = "fixed-clock";
73 clock-frequency = <25000000>;
76 arm_timer_clk: arm_timer_clk {
78 compatible = "fixed-clock";
79 clock-frequency = <50000000>;
84 compatible = "simple-bus";
88 interrupt-parent = <&intc>;
91 l2: l2-cache@500c0000 {
92 compatible = "socionext,uniphier-system-cache";
93 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
95 interrupts = <0 174 4>, <0 175 4>;
97 cache-size = <(256 * 1024)>;
99 cache-line-size = <128>;
103 serial0: serial@54006800 {
104 compatible = "socionext,uniphier-uart";
106 reg = <0x54006800 0x40>;
107 interrupts = <0 33 4>;
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_uart0>;
110 clocks = <&peri_clk 0>;
111 clock-frequency = <80000000>;
114 serial1: serial@54006900 {
115 compatible = "socionext,uniphier-uart";
117 reg = <0x54006900 0x40>;
118 interrupts = <0 35 4>;
119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_uart1>;
121 clocks = <&peri_clk 1>;
122 clock-frequency = <80000000>;
125 serial2: serial@54006a00 {
126 compatible = "socionext,uniphier-uart";
128 reg = <0x54006a00 0x40>;
129 interrupts = <0 37 4>;
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_uart2>;
132 clocks = <&peri_clk 2>;
133 clock-frequency = <80000000>;
136 serial3: serial@54006b00 {
137 compatible = "socionext,uniphier-uart";
139 reg = <0x54006b00 0x40>;
140 interrupts = <0 29 4>;
141 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_uart3>;
143 clocks = <&peri_clk 3>;
144 clock-frequency = <80000000>;
147 port0x: gpio@55000008 {
148 compatible = "socionext,uniphier-gpio";
149 reg = <0x55000008 0x8>;
154 port1x: gpio@55000010 {
155 compatible = "socionext,uniphier-gpio";
156 reg = <0x55000010 0x8>;
161 port2x: gpio@55000018 {
162 compatible = "socionext,uniphier-gpio";
163 reg = <0x55000018 0x8>;
168 port3x: gpio@55000020 {
169 compatible = "socionext,uniphier-gpio";
170 reg = <0x55000020 0x8>;
175 port4: gpio@55000028 {
176 compatible = "socionext,uniphier-gpio";
177 reg = <0x55000028 0x8>;
182 port5x: gpio@55000030 {
183 compatible = "socionext,uniphier-gpio";
184 reg = <0x55000030 0x8>;
189 port6x: gpio@55000038 {
190 compatible = "socionext,uniphier-gpio";
191 reg = <0x55000038 0x8>;
196 port7x: gpio@55000040 {
197 compatible = "socionext,uniphier-gpio";
198 reg = <0x55000040 0x8>;
203 port8x: gpio@55000048 {
204 compatible = "socionext,uniphier-gpio";
205 reg = <0x55000048 0x8>;
210 port9x: gpio@55000050 {
211 compatible = "socionext,uniphier-gpio";
212 reg = <0x55000050 0x8>;
217 port10x: gpio@55000058 {
218 compatible = "socionext,uniphier-gpio";
219 reg = <0x55000058 0x8>;
224 port11x: gpio@55000060 {
225 compatible = "socionext,uniphier-gpio";
226 reg = <0x55000060 0x8>;
231 port12x: gpio@55000068 {
232 compatible = "socionext,uniphier-gpio";
233 reg = <0x55000068 0x8>;
238 port13x: gpio@55000070 {
239 compatible = "socionext,uniphier-gpio";
240 reg = <0x55000070 0x8>;
245 port14x: gpio@55000078 {
246 compatible = "socionext,uniphier-gpio";
247 reg = <0x55000078 0x8>;
252 port16x: gpio@55000088 {
253 compatible = "socionext,uniphier-gpio";
254 reg = <0x55000088 0x8>;
260 compatible = "socionext,uniphier-i2c";
262 reg = <0x58400000 0x40>;
263 #address-cells = <1>;
265 interrupts = <0 41 1>;
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_i2c0>;
268 clocks = <&peri_clk 4>;
269 clock-frequency = <100000>;
273 compatible = "socionext,uniphier-i2c";
275 reg = <0x58480000 0x40>;
276 #address-cells = <1>;
278 interrupts = <0 42 1>;
279 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_i2c1>;
281 clocks = <&peri_clk 5>;
282 clock-frequency = <100000>;
285 /* chip-internal connection for DMD */
287 compatible = "socionext,uniphier-i2c";
288 reg = <0x58500000 0x40>;
289 #address-cells = <1>;
291 interrupts = <0 43 1>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&pinctrl_i2c2>;
294 clocks = <&peri_clk 6>;
295 clock-frequency = <400000>;
299 compatible = "socionext,uniphier-i2c";
301 reg = <0x58580000 0x40>;
302 #address-cells = <1>;
304 interrupts = <0 44 1>;
305 pinctrl-names = "default";
306 pinctrl-0 = <&pinctrl_i2c3>;
307 clocks = <&peri_clk 7>;
308 clock-frequency = <100000>;
311 system_bus: system-bus@58c00000 {
312 compatible = "socionext,uniphier-system-bus";
314 reg = <0x58c00000 0x400>;
315 #address-cells = <2>;
317 pinctrl-names = "default";
318 pinctrl-0 = <&pinctrl_system_bus>;
322 compatible = "socionext,uniphier-smpctrl";
323 reg = <0x59801000 0x400>;
327 compatible = "socionext,uniphier-sld8-mioctrl",
328 "simple-mfd", "syscon";
329 reg = <0x59810000 0x800>;
332 compatible = "socionext,uniphier-sld8-mio-clock";
337 compatible = "socionext,uniphier-sld8-mio-reset";
343 compatible = "socionext,uniphier-sld8-perictrl",
344 "simple-mfd", "syscon";
345 reg = <0x59820000 0x200>;
348 compatible = "socionext,uniphier-sld8-peri-clock";
353 compatible = "socionext,uniphier-sld8-peri-reset";
359 compatible = "socionext,uniphier-sdhc";
361 reg = <0x5a400000 0x200>;
362 interrupts = <0 76 4>;
363 pinctrl-names = "default", "1.8v";
364 pinctrl-0 = <&pinctrl_sd>;
365 pinctrl-1 = <&pinctrl_sd_1v8>;
366 clocks = <&mio_clk 0>;
367 reset-names = "host", "bridge";
368 resets = <&mio_rst 0>, <&mio_rst 3>;
376 emmc: sdhc@5a500000 {
377 compatible = "socionext,uniphier-sdhc";
379 reg = <0x5a500000 0x200>;
380 interrupts = <0 78 4>;
381 pinctrl-names = "default", "1.8v";
382 pinctrl-0 = <&pinctrl_emmc>;
383 pinctrl-1 = <&pinctrl_emmc_1v8>;
384 clocks = <&mio_clk 1>;
385 reset-names = "host", "bridge";
386 resets = <&mio_rst 1>, <&mio_rst 4>;
394 compatible = "socionext,uniphier-ehci", "generic-ehci";
396 reg = <0x5a800100 0x100>;
397 interrupts = <0 80 4>;
398 pinctrl-names = "default";
399 pinctrl-0 = <&pinctrl_usb0>;
400 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
401 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
406 compatible = "socionext,uniphier-ehci", "generic-ehci";
408 reg = <0x5a810100 0x100>;
409 interrupts = <0 81 4>;
410 pinctrl-names = "default";
411 pinctrl-0 = <&pinctrl_usb1>;
412 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
413 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
418 compatible = "socionext,uniphier-ehci", "generic-ehci";
420 reg = <0x5a820100 0x100>;
421 interrupts = <0 82 4>;
422 pinctrl-names = "default";
423 pinctrl-0 = <&pinctrl_usb2>;
424 clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
425 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
430 compatible = "socionext,uniphier-sld8-soc-glue",
431 "simple-mfd", "syscon";
432 reg = <0x5f800000 0x2000>;
436 compatible = "socionext,uniphier-sld8-pinctrl";
442 compatible = "arm,cortex-a9-global-timer";
443 reg = <0x60000200 0x20>;
444 interrupts = <1 11 0x104>;
445 clocks = <&arm_timer_clk>;
449 compatible = "arm,cortex-a9-twd-timer";
450 reg = <0x60000600 0x20>;
451 interrupts = <1 13 0x104>;
452 clocks = <&arm_timer_clk>;
455 intc: interrupt-controller@60001000 {
456 compatible = "arm,cortex-a9-gic";
457 reg = <0x60001000 0x1000>,
459 #interrupt-cells = <3>;
460 interrupt-controller;
464 compatible = "simple-mfd", "syscon";
465 reg = <0x61830000 0x200>;
469 compatible = "socionext,uniphier-sld8-sysctrl",
470 "simple-mfd", "syscon";
471 reg = <0x61840000 0x10000>;
474 compatible = "socionext,uniphier-sld8-clock";
479 compatible = "socionext,uniphier-sld8-reset";
484 nand: nand@68000000 {
485 compatible = "socionext,uniphier-denali-nand-v5a";
487 reg-names = "nand_data", "denali_reg";
488 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
489 interrupts = <0 65 4>;
490 pinctrl-names = "default";
491 pinctrl-0 = <&pinctrl_nand>;
492 clocks = <&sys_clk 2>;
493 nand-ecc-strength = <8>;
498 /include/ "uniphier-pinctrl.dtsi"