arch/arm/dts/uniphier-sld8.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Device Tree Source for UniPhier sLD8 SoC
   4 //
   5 // Copyright (C) 2015-2016 Socionext Inc.
   6 //   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   7
   8 #include <dt-bindings/gpio/uniphier-gpio.h>
   9
  10 / {
  11         compatible = "socionext,uniphier-sld8";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                         enable-method = "psci";
  24                         next-level-cache = <&l2>;
  25                 };
  26         };
  27
  28         psci {
  29                 compatible = "arm,psci-0.2";
  30                 method = "smc";
  31         };
  32
  33         clocks {
  34                 refclk: ref {
  35                         compatible = "fixed-clock";
  36                         #clock-cells = <0>;
  37                         clock-frequency = <25000000>;
  38                 };
  39
  40                 arm_timer_clk: arm-timer {
  41                         #clock-cells = <0>;
  42                         compatible = "fixed-clock";
  43                         clock-frequency = <50000000>;
  44                 };
  45         };
  46
  47         soc {
  48                 compatible = "simple-bus";
  49                 #address-cells = <1>;
  50                 #size-cells = <1>;
  51                 ranges;
  52                 interrupt-parent = <&intc>;
  53
  54                 l2: l2-cache@500c0000 {
  55                         compatible = "socionext,uniphier-system-cache";
  56                         reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
  57                               <0x506c0000 0x400>;
  58                         interrupts = <0 174 4>, <0 175 4>;
  59                         cache-unified;
  60                         cache-size = <(256 * 1024)>;
  61                         cache-sets = <256>;
  62                         cache-line-size = <128>;
  63                         cache-level = <2>;
  64                 };
  65
  66                 serial0: serial@54006800 {
  67                         compatible = "socionext,uniphier-uart";
  68                         status = "disabled";
  69                         reg = <0x54006800 0x40>;
  70                         interrupts = <0 33 4>;
  71                         pinctrl-names = "default";
  72                         pinctrl-0 = <&pinctrl_uart0>;
  73                         clocks = <&peri_clk 0>;
  74                         clock-frequency = <80000000>;
  75                         resets = <&peri_rst 0>;
  76                 };
  77
  78                 serial1: serial@54006900 {
  79                         compatible = "socionext,uniphier-uart";
  80                         status = "disabled";
  81                         reg = <0x54006900 0x40>;
  82                         interrupts = <0 35 4>;
  83                         pinctrl-names = "default";
  84                         pinctrl-0 = <&pinctrl_uart1>;
  85                         clocks = <&peri_clk 1>;
  86                         clock-frequency = <80000000>;
  87                         resets = <&peri_rst 1>;
  88                 };
  89
  90                 serial2: serial@54006a00 {
  91                         compatible = "socionext,uniphier-uart";
  92                         status = "disabled";
  93                         reg = <0x54006a00 0x40>;
  94                         interrupts = <0 37 4>;
  95                         pinctrl-names = "default";
  96                         pinctrl-0 = <&pinctrl_uart2>;
  97                         clocks = <&peri_clk 2>;
  98                         clock-frequency = <80000000>;
  99                         resets = <&peri_rst 2>;
 100                 };
 101
 102                 serial3: serial@54006b00 {
 103                         compatible = "socionext,uniphier-uart";
 104                         status = "disabled";
 105                         reg = <0x54006b00 0x40>;
 106                         interrupts = <0 29 4>;
 107                         pinctrl-names = "default";
 108                         pinctrl-0 = <&pinctrl_uart3>;
 109                         clocks = <&peri_clk 3>;
 110                         clock-frequency = <80000000>;
 111                         resets = <&peri_rst 3>;
 112                 };
 113
 114                 gpio: gpio@55000000 {
 115                         compatible = "socionext,uniphier-gpio";
 116                         reg = <0x55000000 0x200>;
 117                         interrupt-parent = <&aidet>;
 118                         interrupt-controller;
 119                         #interrupt-cells = <2>;
 120                         gpio-controller;
 121                         #gpio-cells = <2>;
 122                         gpio-ranges = <&pinctrl 0 0 0>,
 123                                       <&pinctrl 104 0 0>,
 124                                       <&pinctrl 112 0 0>;
 125                         gpio-ranges-group-names = "gpio_range0",
 126                                                   "gpio_range1",
 127                                                   "gpio_range2";
 128                         ngpios = <136>;
 129                         socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
 130                 };
 131
 132                 i2c0: i2c@58400000 {
 133                         compatible = "socionext,uniphier-i2c";
 134                         status = "disabled";
 135                         reg = <0x58400000 0x40>;
 136                         #address-cells = <1>;
 137                         #size-cells = <0>;
 138                         interrupts = <0 41 1>;
 139                         pinctrl-names = "default";
 140                         pinctrl-0 = <&pinctrl_i2c0>;
 141                         clocks = <&peri_clk 4>;
 142                         resets = <&peri_rst 4>;
 143                         clock-frequency = <100000>;
 144                 };
 145
 146                 i2c1: i2c@58480000 {
 147                         compatible = "socionext,uniphier-i2c";
 148                         status = "disabled";
 149                         reg = <0x58480000 0x40>;
 150                         #address-cells = <1>;
 151                         #size-cells = <0>;
 152                         interrupts = <0 42 1>;
 153                         pinctrl-names = "default";
 154                         pinctrl-0 = <&pinctrl_i2c1>;
 155                         clocks = <&peri_clk 5>;
 156                         resets = <&peri_rst 5>;
 157                         clock-frequency = <100000>;
 158                 };
 159
 160                 /* chip-internal connection for DMD */
 161                 i2c2: i2c@58500000 {
 162                         compatible = "socionext,uniphier-i2c";
 163                         reg = <0x58500000 0x40>;
 164                         #address-cells = <1>;
 165                         #size-cells = <0>;
 166                         interrupts = <0 43 1>;
 167                         pinctrl-names = "default";
 168                         pinctrl-0 = <&pinctrl_i2c2>;
 169                         clocks = <&peri_clk 6>;
 170                         resets = <&peri_rst 6>;
 171                         clock-frequency = <400000>;
 172                 };
 173
 174                 i2c3: i2c@58580000 {
 175                         compatible = "socionext,uniphier-i2c";
 176                         status = "disabled";
 177                         reg = <0x58580000 0x40>;
 178                         #address-cells = <1>;
 179                         #size-cells = <0>;
 180                         interrupts = <0 44 1>;
 181                         pinctrl-names = "default";
 182                         pinctrl-0 = <&pinctrl_i2c3>;
 183                         clocks = <&peri_clk 7>;
 184                         resets = <&peri_rst 7>;
 185                         clock-frequency = <100000>;
 186                 };
 187
 188                 system_bus: system-bus@58c00000 {
 189                         compatible = "socionext,uniphier-system-bus";
 190                         status = "disabled";
 191                         reg = <0x58c00000 0x400>;
 192                         #address-cells = <2>;
 193                         #size-cells = <1>;
 194                         pinctrl-names = "default";
 195                         pinctrl-0 = <&pinctrl_system_bus>;
 196                 };
 197
 198                 smpctrl@59801000 {
 199                         compatible = "socionext,uniphier-smpctrl";
 200                         reg = <0x59801000 0x400>;
 201                 };
 202
 203                 mioctrl@59810000 {
 204                         compatible = "socionext,uniphier-sld8-mioctrl",
 205                                      "simple-mfd", "syscon";
 206                         reg = <0x59810000 0x800>;
 207
 208                         mio_clk: clock {
 209                                 compatible = "socionext,uniphier-sld8-mio-clock";
 210                                 #clock-cells = <1>;
 211                         };
 212
 213                         mio_rst: reset {
 214                                 compatible = "socionext,uniphier-sld8-mio-reset";
 215                                 #reset-cells = <1>;
 216                         };
 217                 };
 218
 219                 perictrl@59820000 {
 220                         compatible = "socionext,uniphier-sld8-perictrl",
 221                                      "simple-mfd", "syscon";
 222                         reg = <0x59820000 0x200>;
 223
 224                         peri_clk: clock {
 225                                 compatible = "socionext,uniphier-sld8-peri-clock";
 226                                 #clock-cells = <1>;
 227                         };
 228
 229                         peri_rst: reset {
 230                                 compatible = "socionext,uniphier-sld8-peri-reset";
 231                                 #reset-cells = <1>;
 232                         };
 233                 };
 234
 235                 sd: sdhc@5a400000 {
 236                         compatible = "socionext,uniphier-sdhc";
 237                         status = "disabled";
 238                         reg = <0x5a400000 0x200>;
 239                         interrupts = <0 76 4>;
 240                         pinctrl-names = "default", "1.8v";
 241                         pinctrl-0 = <&pinctrl_sd>;
 242                         pinctrl-1 = <&pinctrl_sd_1v8>;
 243                         clocks = <&mio_clk 0>;
 244                         reset-names = "host", "bridge";
 245                         resets = <&mio_rst 0>, <&mio_rst 3>;
 246                         bus-width = <4>;
 247                         cap-sd-highspeed;
 248                         sd-uhs-sdr12;
 249                         sd-uhs-sdr25;
 250                         sd-uhs-sdr50;
 251                 };
 252
 253                 emmc: sdhc@5a500000 {
 254                         compatible = "socionext,uniphier-sdhc";
 255                         status = "disabled";
 256                         reg = <0x5a500000 0x200>;
 257                         interrupts = <0 78 4>;
 258                         pinctrl-names = "default", "1.8v";
 259                         pinctrl-0 = <&pinctrl_emmc>;
 260                         pinctrl-1 = <&pinctrl_emmc_1v8>;
 261                         clocks = <&mio_clk 1>;
 262                         reset-names = "host", "bridge";
 263                         resets = <&mio_rst 1>, <&mio_rst 4>;
 264                         bus-width = <8>;
 265                         non-removable;
 266                         cap-mmc-highspeed;
 267                         cap-mmc-hw-reset;
 268                 };
 269
 270                 usb0: usb@5a800100 {
 271                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 272                         status = "disabled";
 273                         reg = <0x5a800100 0x100>;
 274                         interrupts = <0 80 4>;
 275                         pinctrl-names = "default";
 276                         pinctrl-0 = <&pinctrl_usb0>;
 277                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
 278                                  <&mio_clk 12>;
 279                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 280                                  <&mio_rst 12>;
 281                         has-transaction-translator;
 282                 };
 283
 284                 usb1: usb@5a810100 {
 285                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 286                         status = "disabled";
 287                         reg = <0x5a810100 0x100>;
 288                         interrupts = <0 81 4>;
 289                         pinctrl-names = "default";
 290                         pinctrl-0 = <&pinctrl_usb1>;
 291                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
 292                                  <&mio_clk 13>;
 293                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 294                                  <&mio_rst 13>;
 295                         has-transaction-translator;
 296                 };
 297
 298                 usb2: usb@5a820100 {
 299                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 300                         status = "disabled";
 301                         reg = <0x5a820100 0x100>;
 302                         interrupts = <0 82 4>;
 303                         pinctrl-names = "default";
 304                         pinctrl-0 = <&pinctrl_usb2>;
 305                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
 306                                  <&mio_clk 14>;
 307                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
 308                                  <&mio_rst 14>;
 309                         has-transaction-translator;
 310                 };
 311
 312                 soc-glue@5f800000 {
 313                         compatible = "socionext,uniphier-sld8-soc-glue",
 314                                      "simple-mfd", "syscon";
 315                         reg = <0x5f800000 0x2000>;
 316
 317                         pinctrl: pinctrl {
 318                                 compatible = "socionext,uniphier-sld8-pinctrl";
 319                         };
 320                 };
 321
 322                 soc-glue@5f900000 {
 323                         compatible = "socionext,uniphier-sld8-soc-glue-debug",
 324                                      "simple-mfd";
 325                         #address-cells = <1>;
 326                         #size-cells = <1>;
 327                         ranges = <0 0x5f900000 0x2000>;
 328
 329                         efuse@100 {
 330                                 compatible = "socionext,uniphier-efuse";
 331                                 reg = <0x100 0x28>;
 332                         };
 333
 334                         efuse@200 {
 335                                 compatible = "socionext,uniphier-efuse";
 336                                 reg = <0x200 0x14>;
 337                         };
 338                 };
 339
 340                 timer@60000200 {
 341                         compatible = "arm,cortex-a9-global-timer";
 342                         reg = <0x60000200 0x20>;
 343                         interrupts = <1 11 0x104>;
 344                         clocks = <&arm_timer_clk>;
 345                 };
 346
 347                 timer@60000600 {
 348                         compatible = "arm,cortex-a9-twd-timer";
 349                         reg = <0x60000600 0x20>;
 350                         interrupts = <1 13 0x104>;
 351                         clocks = <&arm_timer_clk>;
 352                 };
 353
 354                 intc: interrupt-controller@60001000 {
 355                         compatible = "arm,cortex-a9-gic";
 356                         reg = <0x60001000 0x1000>,
 357                               <0x60000100 0x100>;
 358                         #interrupt-cells = <3>;
 359                         interrupt-controller;
 360                 };
 361
 362                 aidet: aidet@61830000 {
 363                         compatible = "socionext,uniphier-sld8-aidet";
 364                         reg = <0x61830000 0x200>;
 365                         interrupt-controller;
 366                         #interrupt-cells = <2>;
 367                 };
 368
 369                 sysctrl@61840000 {
 370                         compatible = "socionext,uniphier-sld8-sysctrl",
 371                                      "simple-mfd", "syscon";
 372                         reg = <0x61840000 0x10000>;
 373
 374                         sys_clk: clock {
 375                                 compatible = "socionext,uniphier-sld8-clock";
 376                                 #clock-cells = <1>;
 377                         };
 378
 379                         sys_rst: reset {
 380                                 compatible = "socionext,uniphier-sld8-reset";
 381                                 #reset-cells = <1>;
 382                         };
 383                 };
 384
 385                 nand: nand@68000000 {
 386                         compatible = "socionext,uniphier-denali-nand-v5a";
 387                         status = "disabled";
 388                         reg-names = "nand_data", "denali_reg";
 389                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 390                         interrupts = <0 65 4>;
 391                         pinctrl-names = "default";
 392                         pinctrl-0 = <&pinctrl_nand2cs>;
 393                         clocks = <&sys_clk 2>;
 394                         resets = <&sys_rst 2>;
 395                 };
 396         };
 397 };
 398
 399 #include "uniphier-pinctrl.dtsi"