arch/arm/dts/uniphier-sld8.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Device Tree Source for UniPhier sLD8 SoC
   4 //
   5 // Copyright (C) 2015-2016 Socionext Inc.
   6 //   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   7
   8 #include <dt-bindings/gpio/uniphier-gpio.h>
   9
  10 / {
  11         compatible = "socionext,uniphier-sld8";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                         enable-method = "psci";
  24                         next-level-cache = <&l2>;
  25                 };
  26         };
  27
  28         psci {
  29                 compatible = "arm,psci-0.2";
  30                 method = "smc";
  31         };
  32
  33         clocks {
  34                 refclk: ref {
  35                         compatible = "fixed-clock";
  36                         #clock-cells = <0>;
  37                         clock-frequency = <25000000>;
  38                 };
  39
  40                 arm_timer_clk: arm-timer {
  41                         #clock-cells = <0>;
  42                         compatible = "fixed-clock";
  43                         clock-frequency = <50000000>;
  44                 };
  45         };
  46
  47         soc {
  48                 compatible = "simple-bus";
  49                 #address-cells = <1>;
  50                 #size-cells = <1>;
  51                 ranges;
  52                 interrupt-parent = <&intc>;
  53
  54                 l2: cache-controller@500c0000 {
  55                         compatible = "socionext,uniphier-system-cache";
  56                         reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
  57                               <0x506c0000 0x400>;
  58                         interrupts = <0 174 4>, <0 175 4>;
  59                         cache-unified;
  60                         cache-size = <(256 * 1024)>;
  61                         cache-sets = <256>;
  62                         cache-line-size = <128>;
  63                         cache-level = <2>;
  64                 };
  65
  66                 spi: spi@54006000 {
  67                         compatible = "socionext,uniphier-scssi";
  68                         status = "disabled";
  69                         reg = <0x54006000 0x100>;
  70                         interrupts = <0 39 4>;
  71                         pinctrl-names = "default";
  72                         pinctrl-0 = <&pinctrl_spi0>;
  73                         clocks = <&peri_clk 11>;
  74                         resets = <&peri_rst 11>;
  75                 };
  76
  77                 serial0: serial@54006800 {
  78                         compatible = "socionext,uniphier-uart";
  79                         status = "disabled";
  80                         reg = <0x54006800 0x40>;
  81                         interrupts = <0 33 4>;
  82                         pinctrl-names = "default";
  83                         pinctrl-0 = <&pinctrl_uart0>;
  84                         clocks = <&peri_clk 0>;
  85                         resets = <&peri_rst 0>;
  86                 };
  87
  88                 serial1: serial@54006900 {
  89                         compatible = "socionext,uniphier-uart";
  90                         status = "disabled";
  91                         reg = <0x54006900 0x40>;
  92                         interrupts = <0 35 4>;
  93                         pinctrl-names = "default";
  94                         pinctrl-0 = <&pinctrl_uart1>;
  95                         clocks = <&peri_clk 1>;
  96                         resets = <&peri_rst 1>;
  97                 };
  98
  99                 serial2: serial@54006a00 {
 100                         compatible = "socionext,uniphier-uart";
 101                         status = "disabled";
 102                         reg = <0x54006a00 0x40>;
 103                         interrupts = <0 37 4>;
 104                         pinctrl-names = "default";
 105                         pinctrl-0 = <&pinctrl_uart2>;
 106                         clocks = <&peri_clk 2>;
 107                         resets = <&peri_rst 2>;
 108                 };
 109
 110                 serial3: serial@54006b00 {
 111                         compatible = "socionext,uniphier-uart";
 112                         status = "disabled";
 113                         reg = <0x54006b00 0x40>;
 114                         interrupts = <0 29 4>;
 115                         pinctrl-names = "default";
 116                         pinctrl-0 = <&pinctrl_uart3>;
 117                         clocks = <&peri_clk 3>;
 118                         resets = <&peri_rst 3>;
 119                 };
 120
 121                 gpio: gpio@55000000 {
 122                         compatible = "socionext,uniphier-gpio";
 123                         reg = <0x55000000 0x200>;
 124                         interrupt-parent = <&aidet>;
 125                         interrupt-controller;
 126                         #interrupt-cells = <2>;
 127                         gpio-controller;
 128                         #gpio-cells = <2>;
 129                         gpio-ranges = <&pinctrl 0 0 0>,
 130                                       <&pinctrl 104 0 0>,
 131                                       <&pinctrl 112 0 0>;
 132                         gpio-ranges-group-names = "gpio_range0",
 133                                                   "gpio_range1",
 134                                                   "gpio_range2";
 135                         ngpios = <136>;
 136                         socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
 137                 };
 138
 139                 i2c0: i2c@58400000 {
 140                         compatible = "socionext,uniphier-i2c";
 141                         status = "disabled";
 142                         reg = <0x58400000 0x40>;
 143                         #address-cells = <1>;
 144                         #size-cells = <0>;
 145                         interrupts = <0 41 1>;
 146                         pinctrl-names = "default";
 147                         pinctrl-0 = <&pinctrl_i2c0>;
 148                         clocks = <&peri_clk 4>;
 149                         resets = <&peri_rst 4>;
 150                         clock-frequency = <100000>;
 151                 };
 152
 153                 i2c1: i2c@58480000 {
 154                         compatible = "socionext,uniphier-i2c";
 155                         status = "disabled";
 156                         reg = <0x58480000 0x40>;
 157                         #address-cells = <1>;
 158                         #size-cells = <0>;
 159                         interrupts = <0 42 1>;
 160                         pinctrl-names = "default";
 161                         pinctrl-0 = <&pinctrl_i2c1>;
 162                         clocks = <&peri_clk 5>;
 163                         resets = <&peri_rst 5>;
 164                         clock-frequency = <100000>;
 165                 };
 166
 167                 /* chip-internal connection for DMD */
 168                 i2c2: i2c@58500000 {
 169                         compatible = "socionext,uniphier-i2c";
 170                         reg = <0x58500000 0x40>;
 171                         #address-cells = <1>;
 172                         #size-cells = <0>;
 173                         interrupts = <0 43 1>;
 174                         pinctrl-names = "default";
 175                         pinctrl-0 = <&pinctrl_i2c2>;
 176                         clocks = <&peri_clk 6>;
 177                         resets = <&peri_rst 6>;
 178                         clock-frequency = <400000>;
 179                 };
 180
 181                 i2c3: i2c@58580000 {
 182                         compatible = "socionext,uniphier-i2c";
 183                         status = "disabled";
 184                         reg = <0x58580000 0x40>;
 185                         #address-cells = <1>;
 186                         #size-cells = <0>;
 187                         interrupts = <0 44 1>;
 188                         pinctrl-names = "default";
 189                         pinctrl-0 = <&pinctrl_i2c3>;
 190                         clocks = <&peri_clk 7>;
 191                         resets = <&peri_rst 7>;
 192                         clock-frequency = <100000>;
 193                 };
 194
 195                 system_bus: system-bus@58c00000 {
 196                         compatible = "socionext,uniphier-system-bus";
 197                         status = "disabled";
 198                         reg = <0x58c00000 0x400>;
 199                         #address-cells = <2>;
 200                         #size-cells = <1>;
 201                         pinctrl-names = "default";
 202                         pinctrl-0 = <&pinctrl_system_bus>;
 203                 };
 204
 205                 smpctrl@59801000 {
 206                         compatible = "socionext,uniphier-smpctrl";
 207                         reg = <0x59801000 0x400>;
 208                 };
 209
 210                 mioctrl@59810000 {
 211                         compatible = "socionext,uniphier-sld8-mioctrl",
 212                                      "simple-mfd", "syscon";
 213                         reg = <0x59810000 0x800>;
 214
 215                         mio_clk: clock {
 216                                 compatible = "socionext,uniphier-sld8-mio-clock";
 217                                 #clock-cells = <1>;
 218                         };
 219
 220                         mio_rst: reset {
 221                                 compatible = "socionext,uniphier-sld8-mio-reset";
 222                                 #reset-cells = <1>;
 223                         };
 224                 };
 225
 226                 perictrl@59820000 {
 227                         compatible = "socionext,uniphier-sld8-perictrl",
 228                                      "simple-mfd", "syscon";
 229                         reg = <0x59820000 0x200>;
 230
 231                         peri_clk: clock {
 232                                 compatible = "socionext,uniphier-sld8-peri-clock";
 233                                 #clock-cells = <1>;
 234                         };
 235
 236                         peri_rst: reset {
 237                                 compatible = "socionext,uniphier-sld8-peri-reset";
 238                                 #reset-cells = <1>;
 239                         };
 240                 };
 241
 242                 dmac: dma-controller@5a000000 {
 243                         compatible = "socionext,uniphier-mio-dmac";
 244                         reg = <0x5a000000 0x1000>;
 245                         interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
 246                                      <0 71 4>, <0 72 4>, <0 73 4>;
 247                         clocks = <&mio_clk 7>;
 248                         resets = <&mio_rst 7>;
 249                         #dma-cells = <1>;
 250                 };
 251
 252                 sd: mmc@5a400000 {
 253                         compatible = "socionext,uniphier-sd-v2.91";
 254                         status = "disabled";
 255                         reg = <0x5a400000 0x200>;
 256                         interrupts = <0 76 4>;
 257                         pinctrl-names = "default", "uhs";
 258                         pinctrl-0 = <&pinctrl_sd>;
 259                         pinctrl-1 = <&pinctrl_sd_uhs>;
 260                         clocks = <&mio_clk 0>;
 261                         reset-names = "host", "bridge";
 262                         resets = <&mio_rst 0>, <&mio_rst 3>;
 263                         dma-names = "rx-tx";
 264                         dmas = <&dmac 4>;
 265                         bus-width = <4>;
 266                         cap-sd-highspeed;
 267                         sd-uhs-sdr12;
 268                         sd-uhs-sdr25;
 269                         sd-uhs-sdr50;
 270                 };
 271
 272                 emmc: mmc@5a500000 {
 273                         compatible = "socionext,uniphier-sd-v2.91";
 274                         status = "disabled";
 275                         reg = <0x5a500000 0x200>;
 276                         interrupts = <0 78 4>;
 277                         pinctrl-names = "default";
 278                         pinctrl-0 = <&pinctrl_emmc>;
 279                         clocks = <&mio_clk 1>;
 280                         reset-names = "host", "bridge", "hw";
 281                         resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
 282                         dma-names = "rx-tx";
 283                         dmas = <&dmac 6>;
 284                         bus-width = <8>;
 285                         cap-mmc-highspeed;
 286                         cap-mmc-hw-reset;
 287                         non-removable;
 288                 };
 289
 290                 usb0: usb@5a800100 {
 291                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 292                         status = "disabled";
 293                         reg = <0x5a800100 0x100>;
 294                         interrupts = <0 80 4>;
 295                         pinctrl-names = "default";
 296                         pinctrl-0 = <&pinctrl_usb0>;
 297                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
 298                                  <&mio_clk 12>;
 299                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 300                                  <&mio_rst 12>;
 301                         has-transaction-translator;
 302                 };
 303
 304                 usb1: usb@5a810100 {
 305                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 306                         status = "disabled";
 307                         reg = <0x5a810100 0x100>;
 308                         interrupts = <0 81 4>;
 309                         pinctrl-names = "default";
 310                         pinctrl-0 = <&pinctrl_usb1>;
 311                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
 312                                  <&mio_clk 13>;
 313                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 314                                  <&mio_rst 13>;
 315                         has-transaction-translator;
 316                 };
 317
 318                 usb2: usb@5a820100 {
 319                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 320                         status = "disabled";
 321                         reg = <0x5a820100 0x100>;
 322                         interrupts = <0 82 4>;
 323                         pinctrl-names = "default";
 324                         pinctrl-0 = <&pinctrl_usb2>;
 325                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
 326                                  <&mio_clk 14>;
 327                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
 328                                  <&mio_rst 14>;
 329                         has-transaction-translator;
 330                 };
 331
 332                 soc-glue@5f800000 {
 333                         compatible = "socionext,uniphier-sld8-soc-glue",
 334                                      "simple-mfd", "syscon";
 335                         reg = <0x5f800000 0x2000>;
 336
 337                         pinctrl: pinctrl {
 338                                 compatible = "socionext,uniphier-sld8-pinctrl";
 339                         };
 340                 };
 341
 342                 soc-glue@5f900000 {
 343                         compatible = "socionext,uniphier-sld8-soc-glue-debug",
 344                                      "simple-mfd";
 345                         #address-cells = <1>;
 346                         #size-cells = <1>;
 347                         ranges = <0 0x5f900000 0x2000>;
 348
 349                         efuse@100 {
 350                                 compatible = "socionext,uniphier-efuse";
 351                                 reg = <0x100 0x28>;
 352                         };
 353
 354                         efuse@200 {
 355                                 compatible = "socionext,uniphier-efuse";
 356                                 reg = <0x200 0x14>;
 357                         };
 358                 };
 359
 360                 timer@60000200 {
 361                         compatible = "arm,cortex-a9-global-timer";
 362                         reg = <0x60000200 0x20>;
 363                         interrupts = <1 11 0x104>;
 364                         clocks = <&arm_timer_clk>;
 365                 };
 366
 367                 timer@60000600 {
 368                         compatible = "arm,cortex-a9-twd-timer";
 369                         reg = <0x60000600 0x20>;
 370                         interrupts = <1 13 0x104>;
 371                         clocks = <&arm_timer_clk>;
 372                 };
 373
 374                 intc: interrupt-controller@60001000 {
 375                         compatible = "arm,cortex-a9-gic";
 376                         reg = <0x60001000 0x1000>,
 377                               <0x60000100 0x100>;
 378                         #interrupt-cells = <3>;
 379                         interrupt-controller;
 380                 };
 381
 382                 aidet: interrupt-controller@61830000 {
 383                         compatible = "socionext,uniphier-sld8-aidet";
 384                         reg = <0x61830000 0x200>;
 385                         interrupt-controller;
 386                         #interrupt-cells = <2>;
 387                 };
 388
 389                 sysctrl@61840000 {
 390                         compatible = "socionext,uniphier-sld8-sysctrl",
 391                                      "simple-mfd", "syscon";
 392                         reg = <0x61840000 0x10000>;
 393
 394                         sys_clk: clock {
 395                                 compatible = "socionext,uniphier-sld8-clock";
 396                                 #clock-cells = <1>;
 397                         };
 398
 399                         sys_rst: reset {
 400                                 compatible = "socionext,uniphier-sld8-reset";
 401                                 #reset-cells = <1>;
 402                         };
 403                 };
 404
 405                 nand: nand-controller@68000000 {
 406                         compatible = "socionext,uniphier-denali-nand-v5a";
 407                         status = "disabled";
 408                         reg-names = "nand_data", "denali_reg";
 409                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 410                         interrupts = <0 65 4>;
 411                         pinctrl-names = "default";
 412                         pinctrl-0 = <&pinctrl_nand2cs>;
 413                         clock-names = "nand", "nand_x", "ecc";
 414                         clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
 415                         reset-names = "nand", "reg";
 416                         resets = <&sys_rst 2>, <&sys_rst 2>;
 417                 };
 418         };
 419 };
 420
 421 #include "uniphier-pinctrl.dtsi"