1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier PXs3 SoC
5 // Copyright (C) 2017 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
11 /memreserve/ 0x80000000 0x02000000;
14 compatible = "socionext,uniphier-pxs3";
17 interrupt-parent = <&gic>;
42 compatible = "arm,cortex-a53", "arm,armv8";
44 clocks = <&sys_clk 33>;
45 enable-method = "psci";
46 operating-points-v2 = <&cluster0_opp>;
51 compatible = "arm,cortex-a53", "arm,armv8";
53 clocks = <&sys_clk 33>;
54 enable-method = "psci";
55 operating-points-v2 = <&cluster0_opp>;
60 compatible = "arm,cortex-a53", "arm,armv8";
62 clocks = <&sys_clk 33>;
63 enable-method = "psci";
64 operating-points-v2 = <&cluster0_opp>;
69 compatible = "arm,cortex-a53", "arm,armv8";
71 clocks = <&sys_clk 33>;
72 enable-method = "psci";
73 operating-points-v2 = <&cluster0_opp>;
77 cluster0_opp: opp-table {
78 compatible = "operating-points-v2";
82 opp-hz = /bits/ 64 <250000000>;
83 clock-latency-ns = <300>;
86 opp-hz = /bits/ 64 <325000000>;
87 clock-latency-ns = <300>;
90 opp-hz = /bits/ 64 <500000000>;
91 clock-latency-ns = <300>;
94 opp-hz = /bits/ 64 <650000000>;
95 clock-latency-ns = <300>;
98 opp-hz = /bits/ 64 <666667000>;
99 clock-latency-ns = <300>;
102 opp-hz = /bits/ 64 <866667000>;
103 clock-latency-ns = <300>;
106 opp-hz = /bits/ 64 <1000000000>;
107 clock-latency-ns = <300>;
110 opp-hz = /bits/ 64 <1300000000>;
111 clock-latency-ns = <300>;
116 compatible = "arm,psci-1.0";
122 compatible = "fixed-clock";
124 clock-frequency = <25000000>;
128 emmc_pwrseq: emmc-pwrseq {
129 compatible = "mmc-pwrseq-emmc";
130 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>;
134 compatible = "arm,armv8-timer";
135 interrupts = <1 13 4>,
142 compatible = "simple-bus";
143 #address-cells = <1>;
145 ranges = <0 0 0 0xffffffff>;
148 compatible = "socionext,uniphier-scssi";
150 reg = <0x54006000 0x100>;
151 interrupts = <0 39 4>;
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_spi0>;
154 clocks = <&peri_clk 11>;
155 resets = <&peri_rst 11>;
159 compatible = "socionext,uniphier-scssi";
161 reg = <0x54006100 0x100>;
162 interrupts = <0 216 4>;
163 pinctrl-names = "default";
164 pinctrl-0 = <&pinctrl_spi1>;
165 clocks = <&peri_clk 11>;
166 resets = <&peri_rst 11>;
169 serial0: serial@54006800 {
170 compatible = "socionext,uniphier-uart";
172 reg = <0x54006800 0x40>;
173 interrupts = <0 33 4>;
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_uart0>;
176 clocks = <&peri_clk 0>;
177 resets = <&peri_rst 0>;
180 serial1: serial@54006900 {
181 compatible = "socionext,uniphier-uart";
183 reg = <0x54006900 0x40>;
184 interrupts = <0 35 4>;
185 pinctrl-names = "default";
186 pinctrl-0 = <&pinctrl_uart1>;
187 clocks = <&peri_clk 1>;
188 resets = <&peri_rst 1>;
191 serial2: serial@54006a00 {
192 compatible = "socionext,uniphier-uart";
194 reg = <0x54006a00 0x40>;
195 interrupts = <0 37 4>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_uart2>;
198 clocks = <&peri_clk 2>;
199 resets = <&peri_rst 2>;
202 serial3: serial@54006b00 {
203 compatible = "socionext,uniphier-uart";
205 reg = <0x54006b00 0x40>;
206 interrupts = <0 177 4>;
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_uart3>;
209 clocks = <&peri_clk 3>;
210 resets = <&peri_rst 3>;
213 gpio: gpio@55000000 {
214 compatible = "socionext,uniphier-gpio";
215 reg = <0x55000000 0x200>;
216 interrupt-parent = <&aidet>;
217 interrupt-controller;
218 #interrupt-cells = <2>;
221 gpio-ranges = <&pinctrl 0 0 0>,
224 gpio-ranges-group-names = "gpio_range0",
228 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
233 compatible = "socionext,uniphier-fi2c";
235 reg = <0x58780000 0x80>;
236 #address-cells = <1>;
238 interrupts = <0 41 4>;
239 pinctrl-names = "default";
240 pinctrl-0 = <&pinctrl_i2c0>;
241 clocks = <&peri_clk 4>;
242 resets = <&peri_rst 4>;
243 clock-frequency = <100000>;
247 compatible = "socionext,uniphier-fi2c";
249 reg = <0x58781000 0x80>;
250 #address-cells = <1>;
252 interrupts = <0 42 4>;
253 pinctrl-names = "default";
254 pinctrl-0 = <&pinctrl_i2c1>;
255 clocks = <&peri_clk 5>;
256 resets = <&peri_rst 5>;
257 clock-frequency = <100000>;
261 compatible = "socionext,uniphier-fi2c";
263 reg = <0x58782000 0x80>;
264 #address-cells = <1>;
266 interrupts = <0 43 4>;
267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_i2c2>;
269 clocks = <&peri_clk 6>;
270 resets = <&peri_rst 6>;
271 clock-frequency = <100000>;
275 compatible = "socionext,uniphier-fi2c";
277 reg = <0x58783000 0x80>;
278 #address-cells = <1>;
280 interrupts = <0 44 4>;
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_i2c3>;
283 clocks = <&peri_clk 7>;
284 resets = <&peri_rst 7>;
285 clock-frequency = <100000>;
288 /* chip-internal connection for HDMI */
290 compatible = "socionext,uniphier-fi2c";
291 reg = <0x58786000 0x80>;
292 #address-cells = <1>;
294 interrupts = <0 26 4>;
295 clocks = <&peri_clk 10>;
296 resets = <&peri_rst 10>;
297 clock-frequency = <400000>;
300 system_bus: system-bus@58c00000 {
301 compatible = "socionext,uniphier-system-bus";
303 reg = <0x58c00000 0x400>;
304 #address-cells = <2>;
306 pinctrl-names = "default";
307 pinctrl-0 = <&pinctrl_system_bus>;
311 compatible = "socionext,uniphier-smpctrl";
312 reg = <0x59801000 0x400>;
316 compatible = "socionext,uniphier-pxs3-sdctrl",
317 "simple-mfd", "syscon";
318 reg = <0x59810000 0x400>;
321 compatible = "socionext,uniphier-pxs3-sd-clock";
326 compatible = "socionext,uniphier-pxs3-sd-reset";
332 compatible = "socionext,uniphier-pxs3-perictrl",
333 "simple-mfd", "syscon";
334 reg = <0x59820000 0x200>;
337 compatible = "socionext,uniphier-pxs3-peri-clock";
342 compatible = "socionext,uniphier-pxs3-peri-reset";
347 emmc: sdhc@5a000000 {
348 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
349 reg = <0x5a000000 0x400>;
350 interrupts = <0 78 4>;
351 pinctrl-names = "default";
352 pinctrl-0 = <&pinctrl_emmc>;
353 clocks = <&sys_clk 4>;
354 resets = <&sys_rst 4>;
358 mmc-pwrseq = <&emmc_pwrseq>;
359 cdns,phy-input-delay-legacy = <9>;
360 cdns,phy-input-delay-mmc-highspeed = <2>;
361 cdns,phy-input-delay-mmc-ddr = <3>;
362 cdns,phy-dll-delay-sdclk = <21>;
363 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
367 compatible = "socionext,uniphier-sd-v3.1.1";
369 reg = <0x5a400000 0x800>;
370 interrupts = <0 76 4>;
371 pinctrl-names = "default", "uhs";
372 pinctrl-0 = <&pinctrl_sd>;
373 pinctrl-1 = <&pinctrl_sd_uhs>;
374 clocks = <&sd_clk 0>;
375 reset-names = "host";
376 resets = <&sd_rst 0>;
384 soc_glue: soc-glue@5f800000 {
385 compatible = "socionext,uniphier-pxs3-soc-glue",
386 "simple-mfd", "syscon";
387 reg = <0x5f800000 0x2000>;
390 compatible = "socionext,uniphier-pxs3-pinctrl";
395 compatible = "socionext,uniphier-pxs3-soc-glue-debug",
397 #address-cells = <1>;
399 ranges = <0 0x5f900000 0x2000>;
402 compatible = "socionext,uniphier-efuse";
407 compatible = "socionext,uniphier-efuse";
409 #address-cells = <1>;
413 usb_rterm0: trim@54,4 {
417 usb_rterm1: trim@55,4 {
421 usb_rterm2: trim@58,4 {
425 usb_rterm3: trim@59,4 {
429 usb_sel_t0: trim@54,0 {
433 usb_sel_t1: trim@55,0 {
437 usb_sel_t2: trim@58,0 {
441 usb_sel_t3: trim@59,0 {
445 usb_hs_i0: trim@56,0 {
449 usb_hs_i2: trim@5a,0 {
456 aidet: aidet@5fc20000 {
457 compatible = "socionext,uniphier-pxs3-aidet";
458 reg = <0x5fc20000 0x200>;
459 interrupt-controller;
460 #interrupt-cells = <2>;
463 gic: interrupt-controller@5fe00000 {
464 compatible = "arm,gic-v3";
465 reg = <0x5fe00000 0x10000>, /* GICD */
466 <0x5fe80000 0x80000>; /* GICR */
467 interrupt-controller;
468 #interrupt-cells = <3>;
469 interrupts = <1 9 4>;
473 compatible = "socionext,uniphier-pxs3-sysctrl",
474 "simple-mfd", "syscon";
475 reg = <0x61840000 0x10000>;
478 compatible = "socionext,uniphier-pxs3-clock";
483 compatible = "socionext,uniphier-pxs3-reset";
488 compatible = "socionext,uniphier-wdt";
492 eth0: ethernet@65000000 {
493 compatible = "socionext,uniphier-pxs3-ave4";
495 reg = <0x65000000 0x8500>;
496 interrupts = <0 66 4>;
497 pinctrl-names = "default";
498 pinctrl-0 = <&pinctrl_ether_rgmii>;
499 clock-names = "ether";
500 clocks = <&sys_clk 6>;
501 reset-names = "ether";
502 resets = <&sys_rst 6>;
504 local-mac-address = [00 00 00 00 00 00];
505 socionext,syscon-phy-mode = <&soc_glue 0>;
508 #address-cells = <1>;
513 eth1: ethernet@65200000 {
514 compatible = "socionext,uniphier-pxs3-ave4";
516 reg = <0x65200000 0x8500>;
517 interrupts = <0 67 4>;
518 pinctrl-names = "default";
519 pinctrl-0 = <&pinctrl_ether1_rgmii>;
520 clock-names = "ether";
521 clocks = <&sys_clk 7>;
522 reset-names = "ether";
523 resets = <&sys_rst 7>;
525 local-mac-address = [00 00 00 00 00 00];
526 socionext,syscon-phy-mode = <&soc_glue 1>;
529 #address-cells = <1>;
534 _usb0: usb@65a00000 {
535 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
537 reg = <0x65a00000 0xcd00>;
538 interrupt-names = "host", "peripheral";
539 interrupts = <0 134 4>, <0 135 4>;
540 pinctrl-names = "default";
541 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
542 clock-names = "ref", "bus_early", "suspend";
543 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
544 resets = <&usb0_rst 15>;
545 phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
546 <&usb0_ssphy0>, <&usb0_ssphy1>;
551 compatible = "socionext,uniphier-pxs3-dwc3-glue",
553 #address-cells = <1>;
555 ranges = <0 0x65b00000 0x400>;
558 compatible = "socionext,uniphier-pxs3-usb3-reset";
561 clock-names = "link";
562 clocks = <&sys_clk 12>;
563 reset-names = "link";
564 resets = <&sys_rst 12>;
567 usb0_vbus0: regulator@100 {
568 compatible = "socionext,uniphier-pxs3-usb3-regulator";
570 clock-names = "link";
571 clocks = <&sys_clk 12>;
572 reset-names = "link";
573 resets = <&sys_rst 12>;
576 usb0_vbus1: regulator@110 {
577 compatible = "socionext,uniphier-pxs3-usb3-regulator";
579 clock-names = "link";
580 clocks = <&sys_clk 12>;
581 reset-names = "link";
582 resets = <&sys_rst 12>;
585 usb0_hsphy0: hs-phy@200 {
586 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
589 clock-names = "link", "phy";
590 clocks = <&sys_clk 12>, <&sys_clk 16>;
591 reset-names = "link", "phy";
592 resets = <&sys_rst 12>, <&sys_rst 16>;
593 vbus-supply = <&usb0_vbus0>;
594 nvmem-cell-names = "rterm", "sel_t", "hs_i";
595 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
599 usb0_hsphy1: hs-phy@210 {
600 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
603 clock-names = "link", "phy";
604 clocks = <&sys_clk 12>, <&sys_clk 16>;
605 reset-names = "link", "phy";
606 resets = <&sys_rst 12>, <&sys_rst 16>;
607 vbus-supply = <&usb0_vbus1>;
608 nvmem-cell-names = "rterm", "sel_t", "hs_i";
609 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
613 usb0_ssphy0: ss-phy@300 {
614 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
617 clock-names = "link", "phy";
618 clocks = <&sys_clk 12>, <&sys_clk 17>;
619 reset-names = "link", "phy";
620 resets = <&sys_rst 12>, <&sys_rst 17>;
621 vbus-supply = <&usb0_vbus0>;
624 usb0_ssphy1: ss-phy@310 {
625 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
628 clock-names = "link", "phy";
629 clocks = <&sys_clk 12>, <&sys_clk 18>;
630 reset-names = "link", "phy";
631 resets = <&sys_rst 12>, <&sys_rst 18>;
632 vbus-supply = <&usb0_vbus1>;
636 /* FIXME: U-Boot own node */
638 compatible = "socionext,uniphier-pxs3-dwc3";
640 reg = <0x65b00000 0x1000>;
641 #address-cells = <1>;
644 pinctrl-names = "default";
645 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
647 compatible = "snps,dwc3";
648 reg = <0x65a00000 0x10000>;
649 interrupts = <0 134 4>;
655 _usb1: usb@65c00000 {
656 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
658 reg = <0x65c00000 0xcd00>;
659 interrupt-names = "host", "peripheral";
660 interrupts = <0 137 4>, <0 138 4>;
661 pinctrl-names = "default";
662 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
663 clock-names = "ref", "bus_early", "suspend";
664 clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>;
665 resets = <&usb1_rst 15>;
666 phys = <&usb1_hsphy0>, <&usb1_hsphy1>,
672 compatible = "socionext,uniphier-pxs3-dwc3-glue",
674 #address-cells = <1>;
676 ranges = <0 0x65d00000 0x400>;
679 compatible = "socionext,uniphier-pxs3-usb3-reset";
682 clock-names = "link";
683 clocks = <&sys_clk 13>;
684 reset-names = "link";
685 resets = <&sys_rst 13>;
688 usb1_vbus0: regulator@100 {
689 compatible = "socionext,uniphier-pxs3-usb3-regulator";
691 clock-names = "link";
692 clocks = <&sys_clk 13>;
693 reset-names = "link";
694 resets = <&sys_rst 13>;
697 usb1_vbus1: regulator@110 {
698 compatible = "socionext,uniphier-pxs3-usb3-regulator";
700 clock-names = "link";
701 clocks = <&sys_clk 13>;
702 reset-names = "link";
703 resets = <&sys_rst 13>;
706 usb1_hsphy0: hs-phy@200 {
707 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
710 clock-names = "link", "phy", "phy-ext";
711 clocks = <&sys_clk 13>, <&sys_clk 20>,
713 reset-names = "link", "phy";
714 resets = <&sys_rst 13>, <&sys_rst 20>;
715 vbus-supply = <&usb1_vbus0>;
716 nvmem-cell-names = "rterm", "sel_t", "hs_i";
717 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
721 usb1_hsphy1: hs-phy@210 {
722 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
725 clock-names = "link", "phy", "phy-ext";
726 clocks = <&sys_clk 13>, <&sys_clk 20>,
728 reset-names = "link", "phy";
729 resets = <&sys_rst 13>, <&sys_rst 20>;
730 vbus-supply = <&usb1_vbus1>;
731 nvmem-cell-names = "rterm", "sel_t", "hs_i";
732 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
736 usb1_ssphy0: ss-phy@300 {
737 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
740 clock-names = "link", "phy", "phy-ext";
741 clocks = <&sys_clk 13>, <&sys_clk 21>,
743 reset-names = "link", "phy";
744 resets = <&sys_rst 13>, <&sys_rst 21>;
745 vbus-supply = <&usb1_vbus0>;
749 /* FIXME: U-Boot own node */
751 compatible = "socionext,uniphier-pxs3-dwc3";
753 reg = <0x65d00000 0x1000>;
754 #address-cells = <1>;
757 pinctrl-names = "default";
758 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
760 compatible = "snps,dwc3";
761 reg = <0x65c00000 0x10000>;
762 interrupts = <0 137 4>;
768 nand: nand@68000000 {
769 compatible = "socionext,uniphier-denali-nand-v5b";
771 reg-names = "nand_data", "denali_reg";
772 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
773 interrupts = <0 65 4>;
774 pinctrl-names = "default";
775 pinctrl-0 = <&pinctrl_nand>;
776 clock-names = "nand", "nand_x", "ecc";
777 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
778 resets = <&sys_rst 2>;
783 #include "uniphier-pinctrl.dtsi"