1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier PXs3 SoC
5 // Copyright (C) 2017 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
12 compatible = "socionext,uniphier-pxs3";
15 interrupt-parent = <&gic>;
40 compatible = "arm,cortex-a53";
42 clocks = <&sys_clk 33>;
43 enable-method = "psci";
44 operating-points-v2 = <&cluster0_opp>;
49 compatible = "arm,cortex-a53";
51 clocks = <&sys_clk 33>;
52 enable-method = "psci";
53 operating-points-v2 = <&cluster0_opp>;
58 compatible = "arm,cortex-a53";
60 clocks = <&sys_clk 33>;
61 enable-method = "psci";
62 operating-points-v2 = <&cluster0_opp>;
67 compatible = "arm,cortex-a53";
69 clocks = <&sys_clk 33>;
70 enable-method = "psci";
71 operating-points-v2 = <&cluster0_opp>;
75 cluster0_opp: opp-table {
76 compatible = "operating-points-v2";
80 opp-hz = /bits/ 64 <250000000>;
81 clock-latency-ns = <300>;
84 opp-hz = /bits/ 64 <325000000>;
85 clock-latency-ns = <300>;
88 opp-hz = /bits/ 64 <500000000>;
89 clock-latency-ns = <300>;
92 opp-hz = /bits/ 64 <650000000>;
93 clock-latency-ns = <300>;
96 opp-hz = /bits/ 64 <666667000>;
97 clock-latency-ns = <300>;
100 opp-hz = /bits/ 64 <866667000>;
101 clock-latency-ns = <300>;
104 opp-hz = /bits/ 64 <1000000000>;
105 clock-latency-ns = <300>;
108 opp-hz = /bits/ 64 <1300000000>;
109 clock-latency-ns = <300>;
114 compatible = "arm,psci-1.0";
120 compatible = "fixed-clock";
122 clock-frequency = <25000000>;
126 emmc_pwrseq: emmc-pwrseq {
127 compatible = "mmc-pwrseq-emmc";
128 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>;
132 compatible = "arm,armv8-timer";
133 interrupts = <1 13 4>,
140 #address-cells = <2>;
144 secure-memory@81000000 {
145 reg = <0x0 0x81000000 0x0 0x01000000>;
151 compatible = "simple-bus";
152 #address-cells = <1>;
154 ranges = <0 0 0 0xffffffff>;
157 compatible = "socionext,uniphier-scssi";
159 reg = <0x54006000 0x100>;
160 interrupts = <0 39 4>;
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_spi0>;
163 clocks = <&peri_clk 11>;
164 resets = <&peri_rst 11>;
168 compatible = "socionext,uniphier-scssi";
170 reg = <0x54006100 0x100>;
171 interrupts = <0 216 4>;
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_spi1>;
174 clocks = <&peri_clk 11>;
175 resets = <&peri_rst 11>;
178 serial0: serial@54006800 {
179 compatible = "socionext,uniphier-uart";
181 reg = <0x54006800 0x40>;
182 interrupts = <0 33 4>;
183 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_uart0>;
185 clocks = <&peri_clk 0>;
186 resets = <&peri_rst 0>;
189 serial1: serial@54006900 {
190 compatible = "socionext,uniphier-uart";
192 reg = <0x54006900 0x40>;
193 interrupts = <0 35 4>;
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_uart1>;
196 clocks = <&peri_clk 1>;
197 resets = <&peri_rst 1>;
200 serial2: serial@54006a00 {
201 compatible = "socionext,uniphier-uart";
203 reg = <0x54006a00 0x40>;
204 interrupts = <0 37 4>;
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_uart2>;
207 clocks = <&peri_clk 2>;
208 resets = <&peri_rst 2>;
211 serial3: serial@54006b00 {
212 compatible = "socionext,uniphier-uart";
214 reg = <0x54006b00 0x40>;
215 interrupts = <0 177 4>;
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_uart3>;
218 clocks = <&peri_clk 3>;
219 resets = <&peri_rst 3>;
222 gpio: gpio@55000000 {
223 compatible = "socionext,uniphier-gpio";
224 reg = <0x55000000 0x200>;
225 interrupt-parent = <&aidet>;
226 interrupt-controller;
227 #interrupt-cells = <2>;
230 gpio-ranges = <&pinctrl 0 0 0>,
233 gpio-ranges-group-names = "gpio_range0",
237 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
242 compatible = "socionext,uniphier-fi2c";
244 reg = <0x58780000 0x80>;
245 #address-cells = <1>;
247 interrupts = <0 41 4>;
248 pinctrl-names = "default";
249 pinctrl-0 = <&pinctrl_i2c0>;
250 clocks = <&peri_clk 4>;
251 resets = <&peri_rst 4>;
252 clock-frequency = <100000>;
256 compatible = "socionext,uniphier-fi2c";
258 reg = <0x58781000 0x80>;
259 #address-cells = <1>;
261 interrupts = <0 42 4>;
262 pinctrl-names = "default";
263 pinctrl-0 = <&pinctrl_i2c1>;
264 clocks = <&peri_clk 5>;
265 resets = <&peri_rst 5>;
266 clock-frequency = <100000>;
270 compatible = "socionext,uniphier-fi2c";
272 reg = <0x58782000 0x80>;
273 #address-cells = <1>;
275 interrupts = <0 43 4>;
276 pinctrl-names = "default";
277 pinctrl-0 = <&pinctrl_i2c2>;
278 clocks = <&peri_clk 6>;
279 resets = <&peri_rst 6>;
280 clock-frequency = <100000>;
284 compatible = "socionext,uniphier-fi2c";
286 reg = <0x58783000 0x80>;
287 #address-cells = <1>;
289 interrupts = <0 44 4>;
290 pinctrl-names = "default";
291 pinctrl-0 = <&pinctrl_i2c3>;
292 clocks = <&peri_clk 7>;
293 resets = <&peri_rst 7>;
294 clock-frequency = <100000>;
297 /* chip-internal connection for HDMI */
299 compatible = "socionext,uniphier-fi2c";
300 reg = <0x58786000 0x80>;
301 #address-cells = <1>;
303 interrupts = <0 26 4>;
304 clocks = <&peri_clk 10>;
305 resets = <&peri_rst 10>;
306 clock-frequency = <400000>;
309 system_bus: system-bus@58c00000 {
310 compatible = "socionext,uniphier-system-bus";
312 reg = <0x58c00000 0x400>;
313 #address-cells = <2>;
315 pinctrl-names = "default";
316 pinctrl-0 = <&pinctrl_system_bus>;
320 compatible = "socionext,uniphier-smpctrl";
321 reg = <0x59801000 0x400>;
325 compatible = "socionext,uniphier-pxs3-sdctrl",
326 "simple-mfd", "syscon";
327 reg = <0x59810000 0x400>;
330 compatible = "socionext,uniphier-pxs3-sd-clock";
335 compatible = "socionext,uniphier-pxs3-sd-reset";
341 compatible = "socionext,uniphier-pxs3-perictrl",
342 "simple-mfd", "syscon";
343 reg = <0x59820000 0x200>;
346 compatible = "socionext,uniphier-pxs3-peri-clock";
351 compatible = "socionext,uniphier-pxs3-peri-reset";
356 emmc: sdhc@5a000000 {
357 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
358 reg = <0x5a000000 0x400>;
359 interrupts = <0 78 4>;
360 pinctrl-names = "default";
361 pinctrl-0 = <&pinctrl_emmc>;
362 clocks = <&sys_clk 4>;
363 resets = <&sys_rst 4>;
367 mmc-pwrseq = <&emmc_pwrseq>;
368 cdns,phy-input-delay-legacy = <9>;
369 cdns,phy-input-delay-mmc-highspeed = <2>;
370 cdns,phy-input-delay-mmc-ddr = <3>;
371 cdns,phy-dll-delay-sdclk = <21>;
372 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
376 compatible = "socionext,uniphier-sd-v3.1.1";
378 reg = <0x5a400000 0x800>;
379 interrupts = <0 76 4>;
380 pinctrl-names = "default", "uhs";
381 pinctrl-0 = <&pinctrl_sd>;
382 pinctrl-1 = <&pinctrl_sd_uhs>;
383 clocks = <&sd_clk 0>;
384 reset-names = "host";
385 resets = <&sd_rst 0>;
393 soc_glue: soc-glue@5f800000 {
394 compatible = "socionext,uniphier-pxs3-soc-glue",
395 "simple-mfd", "syscon";
396 reg = <0x5f800000 0x2000>;
399 compatible = "socionext,uniphier-pxs3-pinctrl";
404 compatible = "socionext,uniphier-pxs3-soc-glue-debug",
406 #address-cells = <1>;
408 ranges = <0 0x5f900000 0x2000>;
411 compatible = "socionext,uniphier-efuse";
416 compatible = "socionext,uniphier-efuse";
418 #address-cells = <1>;
422 usb_rterm0: trim@54,4 {
426 usb_rterm1: trim@55,4 {
430 usb_rterm2: trim@58,4 {
434 usb_rterm3: trim@59,4 {
438 usb_sel_t0: trim@54,0 {
442 usb_sel_t1: trim@55,0 {
446 usb_sel_t2: trim@58,0 {
450 usb_sel_t3: trim@59,0 {
454 usb_hs_i0: trim@56,0 {
458 usb_hs_i2: trim@5a,0 {
465 aidet: aidet@5fc20000 {
466 compatible = "socionext,uniphier-pxs3-aidet";
467 reg = <0x5fc20000 0x200>;
468 interrupt-controller;
469 #interrupt-cells = <2>;
472 gic: interrupt-controller@5fe00000 {
473 compatible = "arm,gic-v3";
474 reg = <0x5fe00000 0x10000>, /* GICD */
475 <0x5fe80000 0x80000>; /* GICR */
476 interrupt-controller;
477 #interrupt-cells = <3>;
478 interrupts = <1 9 4>;
482 compatible = "socionext,uniphier-pxs3-sysctrl",
483 "simple-mfd", "syscon";
484 reg = <0x61840000 0x10000>;
487 compatible = "socionext,uniphier-pxs3-clock";
492 compatible = "socionext,uniphier-pxs3-reset";
497 compatible = "socionext,uniphier-wdt";
501 eth0: ethernet@65000000 {
502 compatible = "socionext,uniphier-pxs3-ave4";
504 reg = <0x65000000 0x8500>;
505 interrupts = <0 66 4>;
506 pinctrl-names = "default";
507 pinctrl-0 = <&pinctrl_ether_rgmii>;
508 clock-names = "ether";
509 clocks = <&sys_clk 6>;
510 reset-names = "ether";
511 resets = <&sys_rst 6>;
513 local-mac-address = [00 00 00 00 00 00];
514 socionext,syscon-phy-mode = <&soc_glue 0>;
517 #address-cells = <1>;
522 eth1: ethernet@65200000 {
523 compatible = "socionext,uniphier-pxs3-ave4";
525 reg = <0x65200000 0x8500>;
526 interrupts = <0 67 4>;
527 pinctrl-names = "default";
528 pinctrl-0 = <&pinctrl_ether1_rgmii>;
529 clock-names = "ether";
530 clocks = <&sys_clk 7>;
531 reset-names = "ether";
532 resets = <&sys_rst 7>;
534 local-mac-address = [00 00 00 00 00 00];
535 socionext,syscon-phy-mode = <&soc_glue 1>;
538 #address-cells = <1>;
543 _usb0: usb@65a00000 {
544 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
546 reg = <0x65a00000 0xcd00>;
547 interrupt-names = "host", "peripheral";
548 interrupts = <0 134 4>, <0 135 4>;
549 pinctrl-names = "default";
550 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
551 clock-names = "ref", "bus_early", "suspend";
552 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
553 resets = <&usb0_rst 15>;
554 phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
555 <&usb0_ssphy0>, <&usb0_ssphy1>;
560 compatible = "socionext,uniphier-pxs3-dwc3-glue",
562 #address-cells = <1>;
564 ranges = <0 0x65b00000 0x400>;
567 compatible = "socionext,uniphier-pxs3-usb3-reset";
570 clock-names = "link";
571 clocks = <&sys_clk 12>;
572 reset-names = "link";
573 resets = <&sys_rst 12>;
576 usb0_vbus0: regulator@100 {
577 compatible = "socionext,uniphier-pxs3-usb3-regulator";
579 clock-names = "link";
580 clocks = <&sys_clk 12>;
581 reset-names = "link";
582 resets = <&sys_rst 12>;
585 usb0_vbus1: regulator@110 {
586 compatible = "socionext,uniphier-pxs3-usb3-regulator";
588 clock-names = "link";
589 clocks = <&sys_clk 12>;
590 reset-names = "link";
591 resets = <&sys_rst 12>;
594 usb0_hsphy0: hs-phy@200 {
595 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
598 clock-names = "link", "phy";
599 clocks = <&sys_clk 12>, <&sys_clk 16>;
600 reset-names = "link", "phy";
601 resets = <&sys_rst 12>, <&sys_rst 16>;
602 vbus-supply = <&usb0_vbus0>;
603 nvmem-cell-names = "rterm", "sel_t", "hs_i";
604 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
608 usb0_hsphy1: hs-phy@210 {
609 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
612 clock-names = "link", "phy";
613 clocks = <&sys_clk 12>, <&sys_clk 16>;
614 reset-names = "link", "phy";
615 resets = <&sys_rst 12>, <&sys_rst 16>;
616 vbus-supply = <&usb0_vbus1>;
617 nvmem-cell-names = "rterm", "sel_t", "hs_i";
618 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
622 usb0_ssphy0: ss-phy@300 {
623 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
626 clock-names = "link", "phy";
627 clocks = <&sys_clk 12>, <&sys_clk 17>;
628 reset-names = "link", "phy";
629 resets = <&sys_rst 12>, <&sys_rst 17>;
630 vbus-supply = <&usb0_vbus0>;
633 usb0_ssphy1: ss-phy@310 {
634 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
637 clock-names = "link", "phy";
638 clocks = <&sys_clk 12>, <&sys_clk 18>;
639 reset-names = "link", "phy";
640 resets = <&sys_rst 12>, <&sys_rst 18>;
641 vbus-supply = <&usb0_vbus1>;
645 /* FIXME: U-Boot own node */
647 compatible = "socionext,uniphier-pxs3-dwc3";
649 reg = <0x65b00000 0x1000>;
650 #address-cells = <1>;
653 pinctrl-names = "default";
654 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
656 compatible = "snps,dwc3";
657 reg = <0x65a00000 0x10000>;
658 interrupts = <0 134 4>;
664 _usb1: usb@65c00000 {
665 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
667 reg = <0x65c00000 0xcd00>;
668 interrupt-names = "host", "peripheral";
669 interrupts = <0 137 4>, <0 138 4>;
670 pinctrl-names = "default";
671 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
672 clock-names = "ref", "bus_early", "suspend";
673 clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>;
674 resets = <&usb1_rst 15>;
675 phys = <&usb1_hsphy0>, <&usb1_hsphy1>,
681 compatible = "socionext,uniphier-pxs3-dwc3-glue",
683 #address-cells = <1>;
685 ranges = <0 0x65d00000 0x400>;
688 compatible = "socionext,uniphier-pxs3-usb3-reset";
691 clock-names = "link";
692 clocks = <&sys_clk 13>;
693 reset-names = "link";
694 resets = <&sys_rst 13>;
697 usb1_vbus0: regulator@100 {
698 compatible = "socionext,uniphier-pxs3-usb3-regulator";
700 clock-names = "link";
701 clocks = <&sys_clk 13>;
702 reset-names = "link";
703 resets = <&sys_rst 13>;
706 usb1_vbus1: regulator@110 {
707 compatible = "socionext,uniphier-pxs3-usb3-regulator";
709 clock-names = "link";
710 clocks = <&sys_clk 13>;
711 reset-names = "link";
712 resets = <&sys_rst 13>;
715 usb1_hsphy0: hs-phy@200 {
716 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
719 clock-names = "link", "phy", "phy-ext";
720 clocks = <&sys_clk 13>, <&sys_clk 20>,
722 reset-names = "link", "phy";
723 resets = <&sys_rst 13>, <&sys_rst 20>;
724 vbus-supply = <&usb1_vbus0>;
725 nvmem-cell-names = "rterm", "sel_t", "hs_i";
726 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
730 usb1_hsphy1: hs-phy@210 {
731 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
734 clock-names = "link", "phy", "phy-ext";
735 clocks = <&sys_clk 13>, <&sys_clk 20>,
737 reset-names = "link", "phy";
738 resets = <&sys_rst 13>, <&sys_rst 20>;
739 vbus-supply = <&usb1_vbus1>;
740 nvmem-cell-names = "rterm", "sel_t", "hs_i";
741 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
745 usb1_ssphy0: ss-phy@300 {
746 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
749 clock-names = "link", "phy", "phy-ext";
750 clocks = <&sys_clk 13>, <&sys_clk 21>,
752 reset-names = "link", "phy";
753 resets = <&sys_rst 13>, <&sys_rst 21>;
754 vbus-supply = <&usb1_vbus0>;
758 /* FIXME: U-Boot own node */
760 compatible = "socionext,uniphier-pxs3-dwc3";
762 reg = <0x65d00000 0x1000>;
763 #address-cells = <1>;
766 pinctrl-names = "default";
767 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
769 compatible = "snps,dwc3";
770 reg = <0x65c00000 0x10000>;
771 interrupts = <0 137 4>;
777 pcie: pcie@66000000 {
778 compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
780 reg-names = "dbi", "link", "config";
781 reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
782 <0x2fff0000 0x10000>;
783 #address-cells = <3>;
785 clocks = <&sys_clk 24>;
786 resets = <&sys_rst 24>;
789 bus-range = <0x0 0xff>;
793 <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
794 /* non-prefetchable memory */
795 <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
796 #interrupt-cells = <1>;
797 interrupt-names = "dma", "msi";
798 interrupts = <0 224 4>, <0 225 4>;
799 interrupt-map-mask = <0 0 0 7>;
800 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
801 <0 0 0 2 &pcie_intc 1>, /* INTB */
802 <0 0 0 3 &pcie_intc 2>, /* INTC */
803 <0 0 0 4 &pcie_intc 3>; /* INTD */
804 phy-names = "pcie-phy";
807 pcie_intc: legacy-interrupt-controller {
808 interrupt-controller;
809 #interrupt-cells = <1>;
810 interrupt-parent = <&gic>;
811 interrupts = <0 226 4>;
815 pcie_phy: phy@66038000 {
816 compatible = "socionext,uniphier-pxs3-pcie-phy";
817 reg = <0x66038000 0x4000>;
819 clocks = <&sys_clk 24>;
820 resets = <&sys_rst 24>;
821 socionext,syscon = <&soc_glue>;
824 nand: nand@68000000 {
825 compatible = "socionext,uniphier-denali-nand-v5b";
827 reg-names = "nand_data", "denali_reg";
828 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
829 interrupts = <0 65 4>;
830 pinctrl-names = "default";
831 pinctrl-0 = <&pinctrl_nand>;
832 clock-names = "nand", "nand_x", "ecc";
833 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
834 resets = <&sys_rst 2>;
839 #include "uniphier-pinctrl.dtsi"