1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier PXs2 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/thermal/thermal.h>
12 compatible = "socionext,uniphier-pxs2";
22 compatible = "arm,cortex-a9";
24 clocks = <&sys_clk 32>;
25 enable-method = "psci";
26 next-level-cache = <&l2>;
27 operating-points-v2 = <&cpu_opp>;
33 compatible = "arm,cortex-a9";
35 clocks = <&sys_clk 32>;
36 enable-method = "psci";
37 next-level-cache = <&l2>;
38 operating-points-v2 = <&cpu_opp>;
44 compatible = "arm,cortex-a9";
46 clocks = <&sys_clk 32>;
47 enable-method = "psci";
48 next-level-cache = <&l2>;
49 operating-points-v2 = <&cpu_opp>;
55 compatible = "arm,cortex-a9";
57 clocks = <&sys_clk 32>;
58 enable-method = "psci";
59 next-level-cache = <&l2>;
60 operating-points-v2 = <&cpu_opp>;
66 compatible = "operating-points-v2";
70 opp-hz = /bits/ 64 <100000000>;
71 clock-latency-ns = <300>;
74 opp-hz = /bits/ 64 <150000000>;
75 clock-latency-ns = <300>;
78 opp-hz = /bits/ 64 <200000000>;
79 clock-latency-ns = <300>;
82 opp-hz = /bits/ 64 <300000000>;
83 clock-latency-ns = <300>;
86 opp-hz = /bits/ 64 <400000000>;
87 clock-latency-ns = <300>;
90 opp-hz = /bits/ 64 <600000000>;
91 clock-latency-ns = <300>;
94 opp-hz = /bits/ 64 <800000000>;
95 clock-latency-ns = <300>;
98 opp-hz = /bits/ 64 <1200000000>;
99 clock-latency-ns = <300>;
104 compatible = "arm,psci-0.2";
110 compatible = "fixed-clock";
112 clock-frequency = <25000000>;
115 arm_timer_clk: arm-timer {
117 compatible = "fixed-clock";
118 clock-frequency = <50000000>;
124 polling-delay-passive = <250>; /* 250ms */
125 polling-delay = <1000>; /* 1000ms */
126 thermal-sensors = <&pvtctl>;
130 temperature = <95000>; /* 95C */
134 cpu_alert: cpu-alert {
135 temperature = <85000>; /* 85C */
144 cooling-device = <&cpu0
145 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
152 compatible = "simple-bus";
153 #address-cells = <1>;
156 interrupt-parent = <&intc>;
158 l2: l2-cache@500c0000 {
159 compatible = "socionext,uniphier-system-cache";
160 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
162 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
164 cache-size = <(1280 * 1024)>;
166 cache-line-size = <128>;
171 compatible = "socionext,uniphier-scssi";
173 reg = <0x54006000 0x100>;
174 interrupts = <0 39 4>;
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_spi0>;
177 clocks = <&peri_clk 11>;
178 resets = <&peri_rst 11>;
182 compatible = "socionext,uniphier-scssi";
184 reg = <0x54006100 0x100>;
185 interrupts = <0 216 4>;
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_spi1>;
188 clocks = <&peri_clk 11>;
189 resets = <&peri_rst 11>;
192 serial0: serial@54006800 {
193 compatible = "socionext,uniphier-uart";
195 reg = <0x54006800 0x40>;
196 interrupts = <0 33 4>;
197 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_uart0>;
199 clocks = <&peri_clk 0>;
200 resets = <&peri_rst 0>;
203 serial1: serial@54006900 {
204 compatible = "socionext,uniphier-uart";
206 reg = <0x54006900 0x40>;
207 interrupts = <0 35 4>;
208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_uart1>;
210 clocks = <&peri_clk 1>;
211 resets = <&peri_rst 1>;
214 serial2: serial@54006a00 {
215 compatible = "socionext,uniphier-uart";
217 reg = <0x54006a00 0x40>;
218 interrupts = <0 37 4>;
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_uart2>;
221 clocks = <&peri_clk 2>;
222 resets = <&peri_rst 2>;
225 serial3: serial@54006b00 {
226 compatible = "socionext,uniphier-uart";
228 reg = <0x54006b00 0x40>;
229 interrupts = <0 177 4>;
230 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_uart3>;
232 clocks = <&peri_clk 3>;
233 resets = <&peri_rst 3>;
236 gpio: gpio@55000000 {
237 compatible = "socionext,uniphier-gpio";
238 reg = <0x55000000 0x200>;
239 interrupt-parent = <&aidet>;
240 interrupt-controller;
241 #interrupt-cells = <2>;
244 gpio-ranges = <&pinctrl 0 0 0>,
246 gpio-ranges-group-names = "gpio_range0",
249 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
254 compatible = "socionext,uniphier-pxs2-aio";
255 reg = <0x56000000 0x80000>;
256 interrupts = <0 144 4>;
257 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_ain1>,
266 clocks = <&sys_clk 40>;
268 resets = <&sys_rst 40>;
269 #sound-dai-cells = <1>;
270 socionext,syscon = <&soc_glue>;
287 spdif_port0: port@3 {
288 spdif_hiecout1: endpoint {
292 spdif_port1: port@4 {
293 spdif_iecout1: endpoint {
297 comp_spdif_port0: port@5 {
298 comp_spdif_hiecout1: endpoint {
302 comp_spdif_port1: port@6 {
303 comp_spdif_iecout1: endpoint {
309 compatible = "socionext,uniphier-fi2c";
311 reg = <0x58780000 0x80>;
312 #address-cells = <1>;
314 interrupts = <0 41 4>;
315 pinctrl-names = "default";
316 pinctrl-0 = <&pinctrl_i2c0>;
317 clocks = <&peri_clk 4>;
318 resets = <&peri_rst 4>;
319 clock-frequency = <100000>;
323 compatible = "socionext,uniphier-fi2c";
325 reg = <0x58781000 0x80>;
326 #address-cells = <1>;
328 interrupts = <0 42 4>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_i2c1>;
331 clocks = <&peri_clk 5>;
332 resets = <&peri_rst 5>;
333 clock-frequency = <100000>;
337 compatible = "socionext,uniphier-fi2c";
339 reg = <0x58782000 0x80>;
340 #address-cells = <1>;
342 interrupts = <0 43 4>;
343 pinctrl-names = "default";
344 pinctrl-0 = <&pinctrl_i2c2>;
345 clocks = <&peri_clk 6>;
346 resets = <&peri_rst 6>;
347 clock-frequency = <100000>;
351 compatible = "socionext,uniphier-fi2c";
353 reg = <0x58783000 0x80>;
354 #address-cells = <1>;
356 interrupts = <0 44 4>;
357 pinctrl-names = "default";
358 pinctrl-0 = <&pinctrl_i2c3>;
359 clocks = <&peri_clk 7>;
360 resets = <&peri_rst 7>;
361 clock-frequency = <100000>;
364 /* chip-internal connection for DMD */
366 compatible = "socionext,uniphier-fi2c";
367 reg = <0x58784000 0x80>;
368 #address-cells = <1>;
370 interrupts = <0 45 4>;
371 clocks = <&peri_clk 8>;
372 resets = <&peri_rst 8>;
373 clock-frequency = <400000>;
376 /* chip-internal connection for STM */
378 compatible = "socionext,uniphier-fi2c";
379 reg = <0x58785000 0x80>;
380 #address-cells = <1>;
382 interrupts = <0 25 4>;
383 clocks = <&peri_clk 9>;
384 resets = <&peri_rst 9>;
385 clock-frequency = <400000>;
388 /* chip-internal connection for HDMI */
390 compatible = "socionext,uniphier-fi2c";
391 reg = <0x58786000 0x80>;
392 #address-cells = <1>;
394 interrupts = <0 26 4>;
395 clocks = <&peri_clk 10>;
396 resets = <&peri_rst 10>;
397 clock-frequency = <400000>;
400 system_bus: system-bus@58c00000 {
401 compatible = "socionext,uniphier-system-bus";
403 reg = <0x58c00000 0x400>;
404 #address-cells = <2>;
406 pinctrl-names = "default";
407 pinctrl-0 = <&pinctrl_system_bus>;
411 compatible = "socionext,uniphier-smpctrl";
412 reg = <0x59801000 0x400>;
416 compatible = "socionext,uniphier-pxs2-sdctrl",
417 "simple-mfd", "syscon";
418 reg = <0x59810000 0x400>;
421 compatible = "socionext,uniphier-pxs2-sd-clock";
426 compatible = "socionext,uniphier-pxs2-sd-reset";
432 compatible = "socionext,uniphier-pxs2-perictrl",
433 "simple-mfd", "syscon";
434 reg = <0x59820000 0x200>;
437 compatible = "socionext,uniphier-pxs2-peri-clock";
442 compatible = "socionext,uniphier-pxs2-peri-reset";
447 emmc: sdhc@5a000000 {
448 compatible = "socionext,uniphier-sd-v3.1.1";
450 reg = <0x5a000000 0x800>;
451 interrupts = <0 78 4>;
452 pinctrl-names = "default";
453 pinctrl-0 = <&pinctrl_emmc>;
454 clocks = <&sd_clk 1>;
455 reset-names = "host", "hw";
456 resets = <&sd_rst 1>, <&sd_rst 6>;
464 compatible = "socionext,uniphier-sd-v3.1.1";
466 reg = <0x5a400000 0x800>;
467 interrupts = <0 76 4>;
468 pinctrl-names = "default", "uhs";
469 pinctrl-0 = <&pinctrl_sd>;
470 pinctrl-1 = <&pinctrl_sd_uhs>;
471 clocks = <&sd_clk 0>;
472 reset-names = "host";
473 resets = <&sd_rst 0>;
481 soc_glue: soc-glue@5f800000 {
482 compatible = "socionext,uniphier-pxs2-soc-glue",
483 "simple-mfd", "syscon";
484 reg = <0x5f800000 0x2000>;
487 compatible = "socionext,uniphier-pxs2-pinctrl";
492 compatible = "socionext,uniphier-pxs2-soc-glue-debug",
494 #address-cells = <1>;
496 ranges = <0 0x5f900000 0x2000>;
499 compatible = "socionext,uniphier-efuse";
504 compatible = "socionext,uniphier-efuse";
509 aidet: aidet@5fc20000 {
510 compatible = "socionext,uniphier-pxs2-aidet";
511 reg = <0x5fc20000 0x200>;
512 interrupt-controller;
513 #interrupt-cells = <2>;
517 compatible = "arm,cortex-a9-global-timer";
518 reg = <0x60000200 0x20>;
519 interrupts = <1 11 0xf04>;
520 clocks = <&arm_timer_clk>;
524 compatible = "arm,cortex-a9-twd-timer";
525 reg = <0x60000600 0x20>;
526 interrupts = <1 13 0xf04>;
527 clocks = <&arm_timer_clk>;
530 intc: interrupt-controller@60001000 {
531 compatible = "arm,cortex-a9-gic";
532 reg = <0x60001000 0x1000>,
534 #interrupt-cells = <3>;
535 interrupt-controller;
539 compatible = "socionext,uniphier-pxs2-sysctrl",
540 "simple-mfd", "syscon";
541 reg = <0x61840000 0x10000>;
544 compatible = "socionext,uniphier-pxs2-clock";
549 compatible = "socionext,uniphier-pxs2-reset";
554 compatible = "socionext,uniphier-pxs2-thermal";
555 interrupts = <0 3 4>;
556 #thermal-sensor-cells = <0>;
557 socionext,tmod-calibration = <0x0f86 0x6844>;
561 eth: ethernet@65000000 {
562 compatible = "socionext,uniphier-pxs2-ave4";
564 reg = <0x65000000 0x8500>;
565 interrupts = <0 66 4>;
566 pinctrl-names = "default";
567 pinctrl-0 = <&pinctrl_ether_rgmii>;
568 clock-names = "ether";
569 clocks = <&sys_clk 6>;
570 reset-names = "ether";
571 resets = <&sys_rst 6>;
573 local-mac-address = [00 00 00 00 00 00];
574 socionext,syscon-phy-mode = <&soc_glue 0>;
577 #address-cells = <1>;
582 _usb0: usb@65a00000 {
583 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
585 reg = <0x65a00000 0xcd00>;
586 interrupt-names = "host", "peripheral";
587 interrupts = <0 134 4>, <0 135 4>;
588 pinctrl-names = "default";
589 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
590 clock-names = "ref", "bus_early", "suspend";
591 clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
592 resets = <&usb0_rst 15>;
593 phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
594 <&usb0_ssphy0>, <&usb0_ssphy1>;
599 compatible = "socionext,uniphier-pxs2-dwc3-glue",
601 #address-cells = <1>;
603 ranges = <0 0x65b00000 0x400>;
606 compatible = "socionext,uniphier-pxs2-usb3-reset";
609 clock-names = "link";
610 clocks = <&sys_clk 14>;
611 reset-names = "link";
612 resets = <&sys_rst 14>;
615 usb0_vbus0: regulator@100 {
616 compatible = "socionext,uniphier-pxs2-usb3-regulator";
618 clock-names = "link";
619 clocks = <&sys_clk 14>;
620 reset-names = "link";
621 resets = <&sys_rst 14>;
624 usb0_vbus1: regulator@110 {
625 compatible = "socionext,uniphier-pxs2-usb3-regulator";
627 clock-names = "link";
628 clocks = <&sys_clk 14>;
629 reset-names = "link";
630 resets = <&sys_rst 14>;
633 usb0_hsphy0: hs-phy@200 {
634 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
637 clock-names = "link", "phy";
638 clocks = <&sys_clk 14>, <&sys_clk 16>;
639 reset-names = "link", "phy";
640 resets = <&sys_rst 14>, <&sys_rst 16>;
641 vbus-supply = <&usb0_vbus0>;
644 usb0_hsphy1: hs-phy@210 {
645 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
648 clock-names = "link", "phy";
649 clocks = <&sys_clk 14>, <&sys_clk 16>;
650 reset-names = "link", "phy";
651 resets = <&sys_rst 14>, <&sys_rst 16>;
652 vbus-supply = <&usb0_vbus1>;
655 usb0_ssphy0: ss-phy@300 {
656 compatible = "socionext,uniphier-pxs2-usb3-ssphy";
659 clock-names = "link", "phy";
660 clocks = <&sys_clk 14>, <&sys_clk 17>;
661 reset-names = "link", "phy";
662 resets = <&sys_rst 14>, <&sys_rst 17>;
663 vbus-supply = <&usb0_vbus0>;
666 usb0_ssphy1: ss-phy@310 {
667 compatible = "socionext,uniphier-pxs2-usb3-ssphy";
670 clock-names = "link", "phy";
671 clocks = <&sys_clk 14>, <&sys_clk 18>;
672 reset-names = "link", "phy";
673 resets = <&sys_rst 14>, <&sys_rst 18>;
674 vbus-supply = <&usb0_vbus1>;
678 /* FIXME: U-Boot own node */
680 compatible = "socionext,uniphier-pxs2-dwc3";
682 reg = <0x65b00000 0x1000>;
683 #address-cells = <1>;
686 pinctrl-names = "default";
687 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
689 compatible = "snps,dwc3";
690 reg = <0x65a00000 0x10000>;
691 interrupts = <0 134 4>;
697 _usb1: usb@65c00000 {
698 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
700 reg = <0x65c00000 0xcd00>;
701 interrupt-names = "host", "peripheral";
702 interrupts = <0 137 4>, <0 138 4>;
703 pinctrl-names = "default";
704 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
705 clock-names = "ref", "bus_early", "suspend";
706 clocks = <&sys_clk 15>, <&sys_clk 15>, <&sys_clk 15>;
707 resets = <&usb1_rst 15>;
708 phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>;
713 compatible = "socionext,uniphier-pxs2-dwc3-glue",
715 #address-cells = <1>;
717 ranges = <0 0x65d00000 0x400>;
720 compatible = "socionext,uniphier-pxs2-usb3-reset";
723 clock-names = "link";
724 clocks = <&sys_clk 15>;
725 reset-names = "link";
726 resets = <&sys_rst 15>;
729 usb1_vbus0: regulator@100 {
730 compatible = "socionext,uniphier-pxs2-usb3-regulator";
732 clock-names = "link";
733 clocks = <&sys_clk 15>;
734 reset-names = "link";
735 resets = <&sys_rst 15>;
738 usb1_vbus1: regulator@110 {
739 compatible = "socionext,uniphier-pxs2-usb3-regulator";
741 clock-names = "link";
742 clocks = <&sys_clk 15>;
743 reset-names = "link";
744 resets = <&sys_rst 15>;
747 usb1_hsphy0: hs-phy@200 {
748 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
751 clock-names = "link", "phy";
752 clocks = <&sys_clk 15>, <&sys_clk 20>;
753 reset-names = "link", "phy";
754 resets = <&sys_rst 15>, <&sys_rst 20>;
755 vbus-supply = <&usb1_vbus0>;
758 usb1_hsphy1: hs-phy@210 {
759 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
762 clock-names = "link", "phy";
763 clocks = <&sys_clk 15>, <&sys_clk 20>;
764 reset-names = "link", "phy";
765 resets = <&sys_rst 15>, <&sys_rst 20>;
766 vbus-supply = <&usb1_vbus1>;
769 usb1_ssphy0: ss-phy@300 {
770 compatible = "socionext,uniphier-pxs2-usb3-ssphy";
773 clock-names = "link", "phy";
774 clocks = <&sys_clk 15>, <&sys_clk 21>;
775 reset-names = "link", "phy";
776 resets = <&sys_rst 15>, <&sys_rst 21>;
777 vbus-supply = <&usb1_vbus0>;
781 /* FIXME: U-Boot own node */
783 compatible = "socionext,uniphier-pxs2-dwc3";
785 reg = <0x65d00000 0x1000>;
786 #address-cells = <1>;
789 pinctrl-names = "default";
790 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
792 compatible = "snps,dwc3";
793 reg = <0x65c00000 0x10000>;
794 interrupts = <0 137 4>;
800 nand: nand@68000000 {
801 compatible = "socionext,uniphier-denali-nand-v5b";
803 reg-names = "nand_data", "denali_reg";
804 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
805 interrupts = <0 65 4>;
806 pinctrl-names = "default";
807 pinctrl-0 = <&pinctrl_nand2cs>;
808 clock-names = "nand", "nand_x", "ecc";
809 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
810 resets = <&sys_rst 2>;
815 #include "uniphier-pinctrl.dtsi"