2 * Device Tree Source for UniPhier PXs2 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 compatible = "socionext,uniphier-pxs2";
21 compatible = "arm,cortex-a9";
23 clocks = <&sys_clk 32>;
24 enable-method = "psci";
25 next-level-cache = <&l2>;
26 operating-points-v2 = <&cpu_opp>;
31 compatible = "arm,cortex-a9";
33 clocks = <&sys_clk 32>;
34 enable-method = "psci";
35 next-level-cache = <&l2>;
36 operating-points-v2 = <&cpu_opp>;
41 compatible = "arm,cortex-a9";
43 clocks = <&sys_clk 32>;
44 enable-method = "psci";
45 next-level-cache = <&l2>;
46 operating-points-v2 = <&cpu_opp>;
51 compatible = "arm,cortex-a9";
53 clocks = <&sys_clk 32>;
54 enable-method = "psci";
55 next-level-cache = <&l2>;
56 operating-points-v2 = <&cpu_opp>;
61 compatible = "operating-points-v2";
65 opp-hz = /bits/ 64 <100000000>;
66 clock-latency-ns = <300>;
69 opp-hz = /bits/ 64 <150000000>;
70 clock-latency-ns = <300>;
73 opp-hz = /bits/ 64 <200000000>;
74 clock-latency-ns = <300>;
77 opp-hz = /bits/ 64 <300000000>;
78 clock-latency-ns = <300>;
81 opp-hz = /bits/ 64 <400000000>;
82 clock-latency-ns = <300>;
85 opp-hz = /bits/ 64 <600000000>;
86 clock-latency-ns = <300>;
89 opp-hz = /bits/ 64 <800000000>;
90 clock-latency-ns = <300>;
93 opp-hz = /bits/ 64 <1200000000>;
94 clock-latency-ns = <300>;
99 compatible = "arm,psci-0.2";
105 compatible = "fixed-clock";
107 clock-frequency = <25000000>;
110 arm_timer_clk: arm_timer_clk {
112 compatible = "fixed-clock";
113 clock-frequency = <50000000>;
118 compatible = "simple-bus";
119 #address-cells = <1>;
122 interrupt-parent = <&intc>;
124 l2: l2-cache@500c0000 {
125 compatible = "socionext,uniphier-system-cache";
126 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
128 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
130 cache-size = <(1280 * 1024)>;
132 cache-line-size = <128>;
136 serial0: serial@54006800 {
137 compatible = "socionext,uniphier-uart";
139 reg = <0x54006800 0x40>;
140 interrupts = <0 33 4>;
141 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_uart0>;
143 clocks = <&peri_clk 0>;
144 clock-frequency = <88900000>;
147 serial1: serial@54006900 {
148 compatible = "socionext,uniphier-uart";
150 reg = <0x54006900 0x40>;
151 interrupts = <0 35 4>;
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_uart1>;
154 clocks = <&peri_clk 1>;
155 clock-frequency = <88900000>;
158 serial2: serial@54006a00 {
159 compatible = "socionext,uniphier-uart";
161 reg = <0x54006a00 0x40>;
162 interrupts = <0 37 4>;
163 pinctrl-names = "default";
164 pinctrl-0 = <&pinctrl_uart2>;
165 clocks = <&peri_clk 2>;
166 clock-frequency = <88900000>;
169 serial3: serial@54006b00 {
170 compatible = "socionext,uniphier-uart";
172 reg = <0x54006b00 0x40>;
173 interrupts = <0 177 4>;
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_uart3>;
176 clocks = <&peri_clk 3>;
177 clock-frequency = <88900000>;
180 gpio: gpio@55000000 {
181 compatible = "socionext,uniphier-gpio";
182 reg = <0x55000000 0x200>;
183 interrupt-parent = <&aidet>;
184 interrupt-controller;
185 #interrupt-cells = <2>;
188 gpio-ranges = <&pinctrl 0 0 0>,
190 gpio-ranges-group-names = "gpio_range0",
196 compatible = "socionext,uniphier-fi2c";
198 reg = <0x58780000 0x80>;
199 #address-cells = <1>;
201 interrupts = <0 41 4>;
202 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_i2c0>;
204 clocks = <&peri_clk 4>;
205 clock-frequency = <100000>;
209 compatible = "socionext,uniphier-fi2c";
211 reg = <0x58781000 0x80>;
212 #address-cells = <1>;
214 interrupts = <0 42 4>;
215 pinctrl-names = "default";
216 pinctrl-0 = <&pinctrl_i2c1>;
217 clocks = <&peri_clk 5>;
218 clock-frequency = <100000>;
222 compatible = "socionext,uniphier-fi2c";
224 reg = <0x58782000 0x80>;
225 #address-cells = <1>;
227 interrupts = <0 43 4>;
228 pinctrl-names = "default";
229 pinctrl-0 = <&pinctrl_i2c2>;
230 clocks = <&peri_clk 6>;
231 clock-frequency = <100000>;
235 compatible = "socionext,uniphier-fi2c";
237 reg = <0x58783000 0x80>;
238 #address-cells = <1>;
240 interrupts = <0 44 4>;
241 pinctrl-names = "default";
242 pinctrl-0 = <&pinctrl_i2c3>;
243 clocks = <&peri_clk 7>;
244 clock-frequency = <100000>;
247 /* chip-internal connection for DMD */
249 compatible = "socionext,uniphier-fi2c";
250 reg = <0x58784000 0x80>;
251 #address-cells = <1>;
253 interrupts = <0 45 4>;
254 clocks = <&peri_clk 8>;
255 clock-frequency = <400000>;
258 /* chip-internal connection for STM */
260 compatible = "socionext,uniphier-fi2c";
261 reg = <0x58785000 0x80>;
262 #address-cells = <1>;
264 interrupts = <0 25 4>;
265 clocks = <&peri_clk 9>;
266 clock-frequency = <400000>;
269 /* chip-internal connection for HDMI */
271 compatible = "socionext,uniphier-fi2c";
272 reg = <0x58786000 0x80>;
273 #address-cells = <1>;
275 interrupts = <0 26 4>;
276 clocks = <&peri_clk 10>;
277 clock-frequency = <400000>;
280 system_bus: system-bus@58c00000 {
281 compatible = "socionext,uniphier-system-bus";
283 reg = <0x58c00000 0x400>;
284 #address-cells = <2>;
286 pinctrl-names = "default";
287 pinctrl-0 = <&pinctrl_system_bus>;
291 compatible = "socionext,uniphier-smpctrl";
292 reg = <0x59801000 0x400>;
296 compatible = "socionext,uniphier-pxs2-sdctrl",
297 "simple-mfd", "syscon";
298 reg = <0x59810000 0x400>;
301 compatible = "socionext,uniphier-pxs2-sd-clock";
306 compatible = "socionext,uniphier-pxs2-sd-reset";
312 compatible = "socionext,uniphier-pxs2-perictrl",
313 "simple-mfd", "syscon";
314 reg = <0x59820000 0x200>;
317 compatible = "socionext,uniphier-pxs2-peri-clock";
322 compatible = "socionext,uniphier-pxs2-peri-reset";
327 emmc: sdhc@5a000000 {
328 compatible = "socionext,uniphier-sdhc";
330 reg = <0x5a000000 0x800>;
331 interrupts = <0 78 4>;
332 pinctrl-names = "default";
333 pinctrl-0 = <&pinctrl_emmc>;
334 clocks = <&sd_clk 1>;
335 reset-names = "host";
336 resets = <&sd_rst 1>;
345 compatible = "socionext,uniphier-sdhc";
347 reg = <0x5a400000 0x800>;
348 interrupts = <0 76 4>;
349 pinctrl-names = "default", "1.8v";
350 pinctrl-0 = <&pinctrl_sd>;
351 pinctrl-1 = <&pinctrl_sd_1v8>;
352 clocks = <&sd_clk 0>;
353 reset-names = "host";
354 resets = <&sd_rst 0>;
363 compatible = "socionext,uniphier-pxs2-soc-glue",
364 "simple-mfd", "syscon";
365 reg = <0x5f800000 0x2000>;
368 compatible = "socionext,uniphier-pxs2-pinctrl";
372 aidet: aidet@5fc20000 {
373 compatible = "socionext,uniphier-pxs2-aidet";
374 reg = <0x5fc20000 0x200>;
375 interrupt-controller;
376 #interrupt-cells = <2>;
380 compatible = "arm,cortex-a9-global-timer";
381 reg = <0x60000200 0x20>;
382 interrupts = <1 11 0xf04>;
383 clocks = <&arm_timer_clk>;
387 compatible = "arm,cortex-a9-twd-timer";
388 reg = <0x60000600 0x20>;
389 interrupts = <1 13 0xf04>;
390 clocks = <&arm_timer_clk>;
393 intc: interrupt-controller@60001000 {
394 compatible = "arm,cortex-a9-gic";
395 reg = <0x60001000 0x1000>,
397 #interrupt-cells = <3>;
398 interrupt-controller;
402 compatible = "socionext,uniphier-pxs2-sysctrl",
403 "simple-mfd", "syscon";
404 reg = <0x61840000 0x10000>;
407 compatible = "socionext,uniphier-pxs2-clock";
412 compatible = "socionext,uniphier-pxs2-reset";
418 compatible = "socionext,uniphier-pxs2-dwc3";
420 reg = <0x65b00000 0x1000>;
421 #address-cells = <1>;
424 pinctrl-names = "default";
425 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
427 compatible = "snps,dwc3";
428 reg = <0x65a00000 0x10000>;
429 interrupts = <0 134 4>;
436 compatible = "socionext,uniphier-pxs2-dwc3";
438 reg = <0x65d00000 0x1000>;
439 #address-cells = <1>;
442 pinctrl-names = "default";
443 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
445 compatible = "snps,dwc3";
446 reg = <0x65c00000 0x10000>;
447 interrupts = <0 137 4>;
453 nand: nand@68000000 {
454 compatible = "socionext,uniphier-denali-nand-v5b";
456 reg-names = "nand_data", "denali_reg";
457 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
458 interrupts = <0 65 4>;
459 pinctrl-names = "default";
460 pinctrl-0 = <&pinctrl_nand2cs>;
461 clocks = <&sys_clk 2>;
466 #include "uniphier-pinctrl.dtsi"