2 * Device Tree Source for UniPhier ProXstream2 SoC
4 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+ X11
9 /include/ "uniphier-common32.dtsi"
12 compatible = "socionext,proxstream2";
17 enable-method = "socionext,uniphier-smp";
21 compatible = "arm,cortex-a9";
23 next-level-cache = <&l2>;
28 compatible = "arm,cortex-a9";
30 next-level-cache = <&l2>;
35 compatible = "arm,cortex-a9";
37 next-level-cache = <&l2>;
42 compatible = "arm,cortex-a9";
44 next-level-cache = <&l2>;
49 arm_timer_clk: arm_timer_clk {
51 compatible = "fixed-clock";
52 clock-frequency = <50000000>;
57 compatible = "fixed-clock";
58 clock-frequency = <88900000>;
63 compatible = "fixed-clock";
64 clock-frequency = <50000000>;
70 l2: l2-cache@500c0000 {
71 compatible = "socionext,uniphier-system-cache";
72 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
73 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
75 cache-size = <(1280 * 1024)>;
77 cache-line-size = <128>;
82 compatible = "socionext,uniphier-fi2c";
84 reg = <0x58780000 0x80>;
87 interrupts = <0 41 4>;
88 pinctrl-names = "default";
89 pinctrl-0 = <&pinctrl_i2c0>;
91 clock-frequency = <100000>;
95 compatible = "socionext,uniphier-fi2c";
97 reg = <0x58781000 0x80>;
100 interrupts = <0 42 4>;
101 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_i2c1>;
104 clock-frequency = <100000>;
108 compatible = "socionext,uniphier-fi2c";
110 reg = <0x58782000 0x80>;
111 #address-cells = <1>;
113 pinctrl-names = "default";
114 pinctrl-0 = <&pinctrl_i2c2>;
115 interrupts = <0 43 4>;
117 clock-frequency = <100000>;
121 compatible = "socionext,uniphier-fi2c";
123 reg = <0x58783000 0x80>;
124 #address-cells = <1>;
126 interrupts = <0 44 4>;
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_i2c3>;
130 clock-frequency = <100000>;
133 /* chip-internal connection for DMD */
135 compatible = "socionext,uniphier-fi2c";
136 reg = <0x58784000 0x80>;
137 #address-cells = <1>;
139 interrupts = <0 45 4>;
141 clock-frequency = <400000>;
144 /* chip-internal connection for STM */
146 compatible = "socionext,uniphier-fi2c";
147 reg = <0x58785000 0x80>;
148 #address-cells = <1>;
150 interrupts = <0 25 4>;
152 clock-frequency = <400000>;
155 /* chip-internal connection for HDMI */
157 compatible = "socionext,uniphier-fi2c";
158 reg = <0x58786000 0x80>;
159 #address-cells = <1>;
161 interrupts = <0 26 4>;
163 clock-frequency = <400000>;
167 compatible = "socionext,uniphier-xhci", "generic-xhci";
169 reg = <0x65a00000 0x100>;
170 interrupts = <0 134 4>;
171 pinctrl-names = "default";
172 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
176 compatible = "socionext,uniphier-xhci", "generic-xhci";
178 reg = <0x65c00000 0x100>;
179 interrupts = <0 137 4>;
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
186 clock-frequency = <25000000>;
190 clock-frequency = <88900000>;
194 clock-frequency = <88900000>;
198 clock-frequency = <88900000>;
202 clock-frequency = <88900000>;
206 compatible = "socionext,proxstream2-mioctrl";
207 clock-names = "stdmac";
208 clocks = <&sysctrl 10>;
212 compatible = "socionext,proxstream2-perictrl";
213 clock-names = "uart", "fi2c";
214 clocks = <&sysctrl 3>, <&sysctrl 4>;
218 compatible = "socionext,proxstream2-pinctrl", "syscon";
222 compatible = "socionext,proxstream2-sysctrl";