2 * Device Tree Source for UniPhier ProXstream2 SoC
4 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+ X11
9 /include/ "uniphier-common32.dtsi"
12 compatible = "socionext,proxstream2";
17 enable-method = "socionext,uniphier-smp";
21 compatible = "arm,cortex-a9";
23 next-level-cache = <&l2>;
28 compatible = "arm,cortex-a9";
30 next-level-cache = <&l2>;
35 compatible = "arm,cortex-a9";
37 next-level-cache = <&l2>;
42 compatible = "arm,cortex-a9";
44 next-level-cache = <&l2>;
49 arm_timer_clk: arm_timer_clk {
51 compatible = "fixed-clock";
52 clock-frequency = <50000000>;
57 compatible = "fixed-clock";
58 clock-frequency = <50000000>;
64 l2: l2-cache@500c0000 {
65 compatible = "socionext,uniphier-system-cache";
66 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
67 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
69 cache-size = <(1280 * 1024)>;
71 cache-line-size = <128>;
75 port0x: gpio@55000008 {
76 compatible = "socionext,uniphier-gpio";
77 reg = <0x55000008 0x8>;
82 port1x: gpio@55000010 {
83 compatible = "socionext,uniphier-gpio";
84 reg = <0x55000010 0x8>;
89 port2x: gpio@55000018 {
90 compatible = "socionext,uniphier-gpio";
91 reg = <0x55000018 0x8>;
96 port3x: gpio@55000020 {
97 compatible = "socionext,uniphier-gpio";
98 reg = <0x55000020 0x8>;
103 port4: gpio@55000028 {
104 compatible = "socionext,uniphier-gpio";
105 reg = <0x55000028 0x8>;
110 port5x: gpio@55000030 {
111 compatible = "socionext,uniphier-gpio";
112 reg = <0x55000030 0x8>;
117 port6x: gpio@55000038 {
118 compatible = "socionext,uniphier-gpio";
119 reg = <0x55000038 0x8>;
124 port7x: gpio@55000040 {
125 compatible = "socionext,uniphier-gpio";
126 reg = <0x55000040 0x8>;
131 port8x: gpio@55000048 {
132 compatible = "socionext,uniphier-gpio";
133 reg = <0x55000048 0x8>;
138 port9x: gpio@55000050 {
139 compatible = "socionext,uniphier-gpio";
140 reg = <0x55000050 0x8>;
145 port10x: gpio@55000058 {
146 compatible = "socionext,uniphier-gpio";
147 reg = <0x55000058 0x8>;
152 port12x: gpio@55000068 {
153 compatible = "socionext,uniphier-gpio";
154 reg = <0x55000068 0x8>;
159 port13x: gpio@55000070 {
160 compatible = "socionext,uniphier-gpio";
161 reg = <0x55000070 0x8>;
166 port14x: gpio@55000078 {
167 compatible = "socionext,uniphier-gpio";
168 reg = <0x55000078 0x8>;
173 port15x: gpio@55000080 {
174 compatible = "socionext,uniphier-gpio";
175 reg = <0x55000080 0x8>;
180 port16x: gpio@55000088 {
181 compatible = "socionext,uniphier-gpio";
182 reg = <0x55000088 0x8>;
187 port17x: gpio@550000a0 {
188 compatible = "socionext,uniphier-gpio";
189 reg = <0x550000a0 0x8>;
194 port18x: gpio@550000a8 {
195 compatible = "socionext,uniphier-gpio";
196 reg = <0x550000a8 0x8>;
201 port19x: gpio@550000b0 {
202 compatible = "socionext,uniphier-gpio";
203 reg = <0x550000b0 0x8>;
208 port20x: gpio@550000b8 {
209 compatible = "socionext,uniphier-gpio";
210 reg = <0x550000b8 0x8>;
215 port21x: gpio@550000c0 {
216 compatible = "socionext,uniphier-gpio";
217 reg = <0x550000c0 0x8>;
222 port22x: gpio@550000c8 {
223 compatible = "socionext,uniphier-gpio";
224 reg = <0x550000c8 0x8>;
229 port23x: gpio@550000d0 {
230 compatible = "socionext,uniphier-gpio";
231 reg = <0x550000d0 0x8>;
236 port24x: gpio@550000d8 {
237 compatible = "socionext,uniphier-gpio";
238 reg = <0x550000d8 0x8>;
243 port25x: gpio@550000e0 {
244 compatible = "socionext,uniphier-gpio";
245 reg = <0x550000e0 0x8>;
250 port26x: gpio@550000e8 {
251 compatible = "socionext,uniphier-gpio";
252 reg = <0x550000e8 0x8>;
257 port27x: gpio@550000f0 {
258 compatible = "socionext,uniphier-gpio";
259 reg = <0x550000f0 0x8>;
264 port28x: gpio@550000f8 {
265 compatible = "socionext,uniphier-gpio";
266 reg = <0x550000f8 0x8>;
272 compatible = "socionext,uniphier-fi2c";
274 reg = <0x58780000 0x80>;
275 #address-cells = <1>;
277 interrupts = <0 41 4>;
278 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_i2c0>;
281 clock-frequency = <100000>;
285 compatible = "socionext,uniphier-fi2c";
287 reg = <0x58781000 0x80>;
288 #address-cells = <1>;
290 interrupts = <0 42 4>;
291 pinctrl-names = "default";
292 pinctrl-0 = <&pinctrl_i2c1>;
294 clock-frequency = <100000>;
298 compatible = "socionext,uniphier-fi2c";
300 reg = <0x58782000 0x80>;
301 #address-cells = <1>;
303 pinctrl-names = "default";
304 pinctrl-0 = <&pinctrl_i2c2>;
305 interrupts = <0 43 4>;
307 clock-frequency = <100000>;
311 compatible = "socionext,uniphier-fi2c";
313 reg = <0x58783000 0x80>;
314 #address-cells = <1>;
316 interrupts = <0 44 4>;
317 pinctrl-names = "default";
318 pinctrl-0 = <&pinctrl_i2c3>;
320 clock-frequency = <100000>;
323 /* chip-internal connection for DMD */
325 compatible = "socionext,uniphier-fi2c";
326 reg = <0x58784000 0x80>;
327 #address-cells = <1>;
329 interrupts = <0 45 4>;
331 clock-frequency = <400000>;
334 /* chip-internal connection for STM */
336 compatible = "socionext,uniphier-fi2c";
337 reg = <0x58785000 0x80>;
338 #address-cells = <1>;
340 interrupts = <0 25 4>;
342 clock-frequency = <400000>;
345 /* chip-internal connection for HDMI */
347 compatible = "socionext,uniphier-fi2c";
348 reg = <0x58786000 0x80>;
349 #address-cells = <1>;
351 interrupts = <0 26 4>;
353 clock-frequency = <400000>;
356 emmc: sdhc@5a000000 {
357 compatible = "socionext,uniphier-sdhc";
359 reg = <0x5a000000 0x800>;
360 interrupts = <0 78 4>;
361 pinctrl-names = "default";
362 pinctrl-0 = <&pinctrl_emmc>;
363 clocks = <&mio_clk 1>;
369 compatible = "socionext,uniphier-sdhc";
371 reg = <0x5a400000 0x800>;
372 interrupts = <0 76 4>;
373 pinctrl-names = "default", "1.8v";
374 pinctrl-0 = <&pinctrl_sd>;
375 pinctrl-1 = <&pinctrl_sd_1v8>;
376 clocks = <&mio_clk 0>;
381 compatible = "simple-mfd", "syscon";
382 reg = <0x5fc20000 0x200>;
386 compatible = "socionext,uniphier-xhci", "generic-xhci";
388 reg = <0x65a00000 0x100>;
389 interrupts = <0 134 4>;
390 pinctrl-names = "default";
391 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
395 compatible = "socionext,uniphier-xhci", "generic-xhci";
397 reg = <0x65c00000 0x100>;
398 interrupts = <0 137 4>;
399 pinctrl-names = "default";
400 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
405 clock-frequency = <25000000>;
409 clock-frequency = <88900000>;
413 clock-frequency = <88900000>;
417 clock-frequency = <88900000>;
421 clock-frequency = <88900000>;
425 compatible = "socionext,uniphier-pxs2-mio-clock";
429 compatible = "socionext,uniphier-pxs2-mio-reset";
433 compatible = "socionext,uniphier-pxs2-peri-clock";
437 compatible = "socionext,uniphier-pxs2-peri-reset";
441 compatible = "socionext,uniphier-pxs2-pinctrl";
445 compatible = "socionext,uniphier-pxs2-clock";
449 compatible = "socionext,uniphier-pxs2-reset";