arch/arm/dts/uniphier-proxstream2.dtsi

   1 /*
   2  * Device Tree Source for UniPhier ProXstream2 SoC
   3  *
   4  * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+        X11
   7  */
   8
   9 /include/ "uniphier-common32.dtsi"
  10
  11 / {
  12         compatible = "socionext,proxstream2";
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17                 enable-method = "socionext,uniphier-smp";
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                         next-level-cache = <&l2>;
  24                 };
  25
  26                 cpu@1 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a9";
  29                         reg = <1>;
  30                         next-level-cache = <&l2>;
  31                 };
  32
  33                 cpu@2 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a9";
  36                         reg = <2>;
  37                         next-level-cache = <&l2>;
  38                 };
  39
  40                 cpu@3 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a9";
  43                         reg = <3>;
  44                         next-level-cache = <&l2>;
  45                 };
  46         };
  47
  48         clocks {
  49                 arm_timer_clk: arm_timer_clk {
  50                         #clock-cells = <0>;
  51                         compatible = "fixed-clock";
  52                         clock-frequency = <50000000>;
  53                 };
  54
  55                 i2c_clk: i2c_clk {
  56                         #clock-cells = <0>;
  57                         compatible = "fixed-clock";
  58                         clock-frequency = <50000000>;
  59                 };
  60         };
  61 };
  62
  63 &soc {
  64         l2: l2-cache@500c0000 {
  65                 compatible = "socionext,uniphier-system-cache";
  66                 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
  67                 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
  68                 cache-unified;
  69                 cache-size = <(1280 * 1024)>;
  70                 cache-sets = <512>;
  71                 cache-line-size = <128>;
  72                 cache-level = <2>;
  73         };
  74
  75         port0x: gpio@55000008 {
  76                 compatible = "socionext,uniphier-gpio";
  77                 reg = <0x55000008 0x8>;
  78                 gpio-controller;
  79                 #gpio-cells = <2>;
  80         };
  81
  82         port1x: gpio@55000010 {
  83                 compatible = "socionext,uniphier-gpio";
  84                 reg = <0x55000010 0x8>;
  85                 gpio-controller;
  86                 #gpio-cells = <2>;
  87         };
  88
  89         port2x: gpio@55000018 {
  90                 compatible = "socionext,uniphier-gpio";
  91                 reg = <0x55000018 0x8>;
  92                 gpio-controller;
  93                 #gpio-cells = <2>;
  94         };
  95
  96         port3x: gpio@55000020 {
  97                 compatible = "socionext,uniphier-gpio";
  98                 reg = <0x55000020 0x8>;
  99                 gpio-controller;
 100                 #gpio-cells = <2>;
 101         };
 102
 103         port4: gpio@55000028 {
 104                 compatible = "socionext,uniphier-gpio";
 105                 reg = <0x55000028 0x8>;
 106                 gpio-controller;
 107                 #gpio-cells = <2>;
 108         };
 109
 110         port5x: gpio@55000030 {
 111                 compatible = "socionext,uniphier-gpio";
 112                 reg = <0x55000030 0x8>;
 113                 gpio-controller;
 114                 #gpio-cells = <2>;
 115         };
 116
 117         port6x: gpio@55000038 {
 118                 compatible = "socionext,uniphier-gpio";
 119                 reg = <0x55000038 0x8>;
 120                 gpio-controller;
 121                 #gpio-cells = <2>;
 122         };
 123
 124         port7x: gpio@55000040 {
 125                 compatible = "socionext,uniphier-gpio";
 126                 reg = <0x55000040 0x8>;
 127                 gpio-controller;
 128                 #gpio-cells = <2>;
 129         };
 130
 131         port8x: gpio@55000048 {
 132                 compatible = "socionext,uniphier-gpio";
 133                 reg = <0x55000048 0x8>;
 134                 gpio-controller;
 135                 #gpio-cells = <2>;
 136         };
 137
 138         port9x: gpio@55000050 {
 139                 compatible = "socionext,uniphier-gpio";
 140                 reg = <0x55000050 0x8>;
 141                 gpio-controller;
 142                 #gpio-cells = <2>;
 143         };
 144
 145         port10x: gpio@55000058 {
 146                 compatible = "socionext,uniphier-gpio";
 147                 reg = <0x55000058 0x8>;
 148                 gpio-controller;
 149                 #gpio-cells = <2>;
 150         };
 151
 152         port12x: gpio@55000068 {
 153                 compatible = "socionext,uniphier-gpio";
 154                 reg = <0x55000068 0x8>;
 155                 gpio-controller;
 156                 #gpio-cells = <2>;
 157         };
 158
 159         port13x: gpio@55000070 {
 160                 compatible = "socionext,uniphier-gpio";
 161                 reg = <0x55000070 0x8>;
 162                 gpio-controller;
 163                 #gpio-cells = <2>;
 164         };
 165
 166         port14x: gpio@55000078 {
 167                 compatible = "socionext,uniphier-gpio";
 168                 reg = <0x55000078 0x8>;
 169                 gpio-controller;
 170                 #gpio-cells = <2>;
 171         };
 172
 173         port15x: gpio@55000080 {
 174                 compatible = "socionext,uniphier-gpio";
 175                 reg = <0x55000080 0x8>;
 176                 gpio-controller;
 177                 #gpio-cells = <2>;
 178         };
 179
 180         port16x: gpio@55000088 {
 181                 compatible = "socionext,uniphier-gpio";
 182                 reg = <0x55000088 0x8>;
 183                 gpio-controller;
 184                 #gpio-cells = <2>;
 185         };
 186
 187         port17x: gpio@550000a0 {
 188                 compatible = "socionext,uniphier-gpio";
 189                 reg = <0x550000a0 0x8>;
 190                 gpio-controller;
 191                 #gpio-cells = <2>;
 192         };
 193
 194         port18x: gpio@550000a8 {
 195                 compatible = "socionext,uniphier-gpio";
 196                 reg = <0x550000a8 0x8>;
 197                 gpio-controller;
 198                 #gpio-cells = <2>;
 199         };
 200
 201         port19x: gpio@550000b0 {
 202                 compatible = "socionext,uniphier-gpio";
 203                 reg = <0x550000b0 0x8>;
 204                 gpio-controller;
 205                 #gpio-cells = <2>;
 206         };
 207
 208         port20x: gpio@550000b8 {
 209                 compatible = "socionext,uniphier-gpio";
 210                 reg = <0x550000b8 0x8>;
 211                 gpio-controller;
 212                 #gpio-cells = <2>;
 213         };
 214
 215         port21x: gpio@550000c0 {
 216                 compatible = "socionext,uniphier-gpio";
 217                 reg = <0x550000c0 0x8>;
 218                 gpio-controller;
 219                 #gpio-cells = <2>;
 220         };
 221
 222         port22x: gpio@550000c8 {
 223                 compatible = "socionext,uniphier-gpio";
 224                 reg = <0x550000c8 0x8>;
 225                 gpio-controller;
 226                 #gpio-cells = <2>;
 227         };
 228
 229         port23x: gpio@550000d0 {
 230                 compatible = "socionext,uniphier-gpio";
 231                 reg = <0x550000d0 0x8>;
 232                 gpio-controller;
 233                 #gpio-cells = <2>;
 234         };
 235
 236         port24x: gpio@550000d8 {
 237                 compatible = "socionext,uniphier-gpio";
 238                 reg = <0x550000d8 0x8>;
 239                 gpio-controller;
 240                 #gpio-cells = <2>;
 241         };
 242
 243         port25x: gpio@550000e0 {
 244                 compatible = "socionext,uniphier-gpio";
 245                 reg = <0x550000e0 0x8>;
 246                 gpio-controller;
 247                 #gpio-cells = <2>;
 248         };
 249
 250         port26x: gpio@550000e8 {
 251                 compatible = "socionext,uniphier-gpio";
 252                 reg = <0x550000e8 0x8>;
 253                 gpio-controller;
 254                 #gpio-cells = <2>;
 255         };
 256
 257         port27x: gpio@550000f0 {
 258                 compatible = "socionext,uniphier-gpio";
 259                 reg = <0x550000f0 0x8>;
 260                 gpio-controller;
 261                 #gpio-cells = <2>;
 262         };
 263
 264         port28x: gpio@550000f8 {
 265                 compatible = "socionext,uniphier-gpio";
 266                 reg = <0x550000f8 0x8>;
 267                 gpio-controller;
 268                 #gpio-cells = <2>;
 269         };
 270
 271         i2c0: i2c@58780000 {
 272                 compatible = "socionext,uniphier-fi2c";
 273                 status = "disabled";
 274                 reg = <0x58780000 0x80>;
 275                 #address-cells = <1>;
 276                 #size-cells = <0>;
 277                 interrupts = <0 41 4>;
 278                 pinctrl-names = "default";
 279                 pinctrl-0 = <&pinctrl_i2c0>;
 280                 clocks = <&i2c_clk>;
 281                 clock-frequency = <100000>;
 282         };
 283
 284         i2c1: i2c@58781000 {
 285                 compatible = "socionext,uniphier-fi2c";
 286                 status = "disabled";
 287                 reg = <0x58781000 0x80>;
 288                 #address-cells = <1>;
 289                 #size-cells = <0>;
 290                 interrupts = <0 42 4>;
 291                 pinctrl-names = "default";
 292                 pinctrl-0 = <&pinctrl_i2c1>;
 293                 clocks = <&i2c_clk>;
 294                 clock-frequency = <100000>;
 295         };
 296
 297         i2c2: i2c@58782000 {
 298                 compatible = "socionext,uniphier-fi2c";
 299                 status = "disabled";
 300                 reg = <0x58782000 0x80>;
 301                 #address-cells = <1>;
 302                 #size-cells = <0>;
 303                 pinctrl-names = "default";
 304                 pinctrl-0 = <&pinctrl_i2c2>;
 305                 interrupts = <0 43 4>;
 306                 clocks = <&i2c_clk>;
 307                 clock-frequency = <100000>;
 308         };
 309
 310         i2c3: i2c@58783000 {
 311                 compatible = "socionext,uniphier-fi2c";
 312                 status = "disabled";
 313                 reg = <0x58783000 0x80>;
 314                 #address-cells = <1>;
 315                 #size-cells = <0>;
 316                 interrupts = <0 44 4>;
 317                 pinctrl-names = "default";
 318                 pinctrl-0 = <&pinctrl_i2c3>;
 319                 clocks = <&i2c_clk>;
 320                 clock-frequency = <100000>;
 321         };
 322
 323         /* chip-internal connection for DMD */
 324         i2c4: i2c@58784000 {
 325                 compatible = "socionext,uniphier-fi2c";
 326                 reg = <0x58784000 0x80>;
 327                 #address-cells = <1>;
 328                 #size-cells = <0>;
 329                 interrupts = <0 45 4>;
 330                 clocks = <&i2c_clk>;
 331                 clock-frequency = <400000>;
 332         };
 333
 334         /* chip-internal connection for STM */
 335         i2c5: i2c@58785000 {
 336                 compatible = "socionext,uniphier-fi2c";
 337                 reg = <0x58785000 0x80>;
 338                 #address-cells = <1>;
 339                 #size-cells = <0>;
 340                 interrupts = <0 25 4>;
 341                 clocks = <&i2c_clk>;
 342                 clock-frequency = <400000>;
 343         };
 344
 345         /* chip-internal connection for HDMI */
 346         i2c6: i2c@58786000 {
 347                 compatible = "socionext,uniphier-fi2c";
 348                 reg = <0x58786000 0x80>;
 349                 #address-cells = <1>;
 350                 #size-cells = <0>;
 351                 interrupts = <0 26 4>;
 352                 clocks = <&i2c_clk>;
 353                 clock-frequency = <400000>;
 354         };
 355
 356         emmc: sdhc@5a000000 {
 357                 compatible = "socionext,uniphier-sdhc";
 358                 status = "disabled";
 359                 reg = <0x5a000000 0x800>;
 360                 interrupts = <0 78 4>;
 361                 pinctrl-names = "default";
 362                 pinctrl-0 = <&pinctrl_emmc>;
 363                 clocks = <&mio_clk 1>;
 364                 bus-width = <8>;
 365                 non-removable;
 366         };
 367
 368         sd: sdhc@5a400000 {
 369                 compatible = "socionext,uniphier-sdhc";
 370                 status = "disabled";
 371                 reg = <0x5a400000 0x800>;
 372                 interrupts = <0 76 4>;
 373                 pinctrl-names = "default", "1.8v";
 374                 pinctrl-0 = <&pinctrl_sd>;
 375                 pinctrl-1 = <&pinctrl_sd_1v8>;
 376                 clocks = <&mio_clk 0>;
 377                 bus-width = <4>;
 378         };
 379
 380         aidet@5fc20000 {
 381                 compatible = "simple-mfd", "syscon";
 382                 reg = <0x5fc20000 0x200>;
 383         };
 384
 385         usb0: usb@65a00000 {
 386                 compatible = "socionext,uniphier-xhci", "generic-xhci";
 387                 status = "disabled";
 388                 reg = <0x65a00000 0x100>;
 389                 interrupts = <0 134 4>;
 390                 pinctrl-names = "default";
 391                 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
 392         };
 393
 394         usb1: usb@65c00000 {
 395                 compatible = "socionext,uniphier-xhci", "generic-xhci";
 396                 status = "disabled";
 397                 reg = <0x65c00000 0x100>;
 398                 interrupts = <0 137 4>;
 399                 pinctrl-names = "default";
 400                 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
 401         };
 402 };
 403
 404 &refclk {
 405         clock-frequency = <25000000>;
 406 };
 407
 408 &serial0 {
 409         clock-frequency = <88900000>;
 410 };
 411
 412 &serial1 {
 413         clock-frequency = <88900000>;
 414 };
 415
 416 &serial2 {
 417         clock-frequency = <88900000>;
 418 };
 419
 420 &serial3 {
 421         clock-frequency = <88900000>;
 422 };
 423
 424 &mio_clk {
 425         compatible = "socionext,uniphier-pxs2-mio-clock";
 426 };
 427
 428 &mio_rst {
 429         compatible = "socionext,uniphier-pxs2-mio-reset";
 430 };
 431
 432 &peri_clk {
 433         compatible = "socionext,uniphier-pxs2-peri-clock";
 434 };
 435
 436 &peri_rst {
 437         compatible = "socionext,uniphier-pxs2-peri-reset";
 438 };
 439
 440 &pinctrl {
 441         compatible = "socionext,uniphier-pxs2-pinctrl";
 442 };
 443
 444 &sys_clk {
 445         compatible = "socionext,uniphier-pxs2-clock";
 446 };
 447
 448 &sys_rst {
 449         compatible = "socionext,uniphier-pxs2-reset";
 450 };