2 * Device Tree Source for UniPhier Pro5 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: GPL-2.0+ X11
10 /include/ "uniphier-common32.dtsi"
13 compatible = "socionext,uniphier-pro5";
21 compatible = "arm,cortex-a9";
23 enable-method = "psci";
24 next-level-cache = <&l2>;
29 compatible = "arm,cortex-a9";
31 enable-method = "psci";
32 next-level-cache = <&l2>;
37 arm_timer_clk: arm_timer_clk {
39 compatible = "fixed-clock";
40 clock-frequency = <50000000>;
45 compatible = "fixed-clock";
46 clock-frequency = <50000000>;
52 l2: l2-cache@500c0000 {
53 compatible = "socionext,uniphier-system-cache";
54 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
55 interrupts = <0 190 4>, <0 191 4>;
57 cache-size = <(2 * 1024 * 1024)>;
59 cache-line-size = <128>;
61 next-level-cache = <&l3>;
64 l3: l3-cache@500c8000 {
65 compatible = "socionext,uniphier-system-cache";
66 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
67 interrupts = <0 174 4>, <0 175 4>;
69 cache-size = <(2 * 1024 * 1024)>;
71 cache-line-size = <256>;
75 port0x: gpio@55000008 {
76 compatible = "socionext,uniphier-gpio";
77 reg = <0x55000008 0x8>;
82 port1x: gpio@55000010 {
83 compatible = "socionext,uniphier-gpio";
84 reg = <0x55000010 0x8>;
89 port2x: gpio@55000018 {
90 compatible = "socionext,uniphier-gpio";
91 reg = <0x55000018 0x8>;
96 port3x: gpio@55000020 {
97 compatible = "socionext,uniphier-gpio";
98 reg = <0x55000020 0x8>;
103 port4: gpio@55000028 {
104 compatible = "socionext,uniphier-gpio";
105 reg = <0x55000028 0x8>;
110 port5x: gpio@55000030 {
111 compatible = "socionext,uniphier-gpio";
112 reg = <0x55000030 0x8>;
117 port6x: gpio@55000038 {
118 compatible = "socionext,uniphier-gpio";
119 reg = <0x55000038 0x8>;
124 port7x: gpio@55000040 {
125 compatible = "socionext,uniphier-gpio";
126 reg = <0x55000040 0x8>;
131 port8x: gpio@55000048 {
132 compatible = "socionext,uniphier-gpio";
133 reg = <0x55000048 0x8>;
138 port9x: gpio@55000050 {
139 compatible = "socionext,uniphier-gpio";
140 reg = <0x55000050 0x8>;
145 port10x: gpio@55000058 {
146 compatible = "socionext,uniphier-gpio";
147 reg = <0x55000058 0x8>;
152 port11x: gpio@55000060 {
153 compatible = "socionext,uniphier-gpio";
154 reg = <0x55000060 0x8>;
159 port12x: gpio@55000068 {
160 compatible = "socionext,uniphier-gpio";
161 reg = <0x55000068 0x8>;
166 port13x: gpio@55000070 {
167 compatible = "socionext,uniphier-gpio";
168 reg = <0x55000070 0x8>;
173 port14x: gpio@55000078 {
174 compatible = "socionext,uniphier-gpio";
175 reg = <0x55000078 0x8>;
180 port17x: gpio@550000a0 {
181 compatible = "socionext,uniphier-gpio";
182 reg = <0x550000a0 0x8>;
187 port18x: gpio@550000a8 {
188 compatible = "socionext,uniphier-gpio";
189 reg = <0x550000a8 0x8>;
194 port19x: gpio@550000b0 {
195 compatible = "socionext,uniphier-gpio";
196 reg = <0x550000b0 0x8>;
201 port20x: gpio@550000b8 {
202 compatible = "socionext,uniphier-gpio";
203 reg = <0x550000b8 0x8>;
208 port21x: gpio@550000c0 {
209 compatible = "socionext,uniphier-gpio";
210 reg = <0x550000c0 0x8>;
215 port22x: gpio@550000c8 {
216 compatible = "socionext,uniphier-gpio";
217 reg = <0x550000c8 0x8>;
222 port23x: gpio@550000d0 {
223 compatible = "socionext,uniphier-gpio";
224 reg = <0x550000d0 0x8>;
229 port24x: gpio@550000d8 {
230 compatible = "socionext,uniphier-gpio";
231 reg = <0x550000d8 0x8>;
236 port25x: gpio@550000e0 {
237 compatible = "socionext,uniphier-gpio";
238 reg = <0x550000e0 0x8>;
243 port26x: gpio@550000e8 {
244 compatible = "socionext,uniphier-gpio";
245 reg = <0x550000e8 0x8>;
250 port27x: gpio@550000f0 {
251 compatible = "socionext,uniphier-gpio";
252 reg = <0x550000f0 0x8>;
257 port28x: gpio@550000f8 {
258 compatible = "socionext,uniphier-gpio";
259 reg = <0x550000f8 0x8>;
264 port29x: gpio@55000100 {
265 compatible = "socionext,uniphier-gpio";
266 reg = <0x55000100 0x8>;
271 port30x: gpio@55000108 {
272 compatible = "socionext,uniphier-gpio";
273 reg = <0x55000108 0x8>;
279 compatible = "socionext,uniphier-fi2c";
281 reg = <0x58780000 0x80>;
282 #address-cells = <1>;
284 interrupts = <0 41 4>;
285 pinctrl-names = "default";
286 pinctrl-0 = <&pinctrl_i2c0>;
288 clock-frequency = <100000>;
292 compatible = "socionext,uniphier-fi2c";
294 reg = <0x58781000 0x80>;
295 #address-cells = <1>;
297 interrupts = <0 42 4>;
298 pinctrl-names = "default";
299 pinctrl-0 = <&pinctrl_i2c1>;
301 clock-frequency = <100000>;
305 compatible = "socionext,uniphier-fi2c";
307 reg = <0x58782000 0x80>;
308 #address-cells = <1>;
310 interrupts = <0 43 4>;
311 pinctrl-names = "default";
312 pinctrl-0 = <&pinctrl_i2c2>;
314 clock-frequency = <100000>;
318 compatible = "socionext,uniphier-fi2c";
320 reg = <0x58783000 0x80>;
321 #address-cells = <1>;
323 interrupts = <0 44 4>;
324 pinctrl-names = "default";
325 pinctrl-0 = <&pinctrl_i2c3>;
327 clock-frequency = <100000>;
330 /* i2c4 does not exist */
332 /* chip-internal connection for DMD */
334 compatible = "socionext,uniphier-fi2c";
335 reg = <0x58785000 0x80>;
336 #address-cells = <1>;
338 interrupts = <0 25 4>;
340 clock-frequency = <400000>;
343 /* chip-internal connection for HDMI */
345 compatible = "socionext,uniphier-fi2c";
346 reg = <0x58786000 0x80>;
347 #address-cells = <1>;
349 interrupts = <0 26 4>;
351 clock-frequency = <400000>;
355 compatible = "simple-mfd", "syscon";
356 reg = <0x5fc20000 0x200>;
359 emmc: sdhc@68400000 {
360 compatible = "socionext,uniphier-sdhc";
362 reg = <0x68400000 0x800>;
363 interrupts = <0 78 4>;
364 pinctrl-names = "default";
365 pinctrl-0 = <&pinctrl_emmc>;
366 clocks = <&mio_clk 1>;
367 reset-names = "host", "hw-reset";
368 resets = <&mio_rst 1>, <&mio_rst 6>;
374 compatible = "socionext,uniphier-sdhc";
376 reg = <0x68800000 0x800>;
377 interrupts = <0 76 4>;
378 pinctrl-names = "default", "1.8v";
379 pinctrl-0 = <&pinctrl_sd>;
380 pinctrl-1 = <&pinctrl_sd_1v8>;
381 clocks = <&mio_clk 0>;
382 reset-names = "host";
383 resets = <&mio_rst 0>;
388 compatible = "socionext,uniphier-xhci", "generic-xhci";
390 reg = <0x65a00000 0x100>;
391 interrupts = <0 134 4>;
392 pinctrl-names = "default";
393 pinctrl-0 = <&pinctrl_usb0>;
397 compatible = "socionext,uniphier-xhci", "generic-xhci";
399 reg = <0x65c00000 0x100>;
400 interrupts = <0 137 4>;
401 pinctrl-names = "default";
402 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
407 clock-frequency = <20000000>;
411 clock-frequency = <73728000>;
415 clock-frequency = <73728000>;
419 clock-frequency = <73728000>;
423 clock-frequency = <73728000>;
427 compatible = "socionext,uniphier-pro5-mio-clock";
431 compatible = "socionext,uniphier-pro5-mio-reset";
435 compatible = "socionext,uniphier-pro5-peri-clock";
439 compatible = "socionext,uniphier-pro5-peri-reset";
443 compatible = "socionext,uniphier-pro5-pinctrl";
447 compatible = "socionext,uniphier-pro5-clock";
451 compatible = "socionext,uniphier-pro5-reset";