2 * Device Tree Source for UniPhier Pro5 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 compatible = "socionext,uniphier-pro5";
21 compatible = "arm,cortex-a9";
23 clocks = <&sys_clk 32>;
24 enable-method = "psci";
25 next-level-cache = <&l2>;
26 operating-points-v2 = <&cpu_opp>;
31 compatible = "arm,cortex-a9";
33 clocks = <&sys_clk 32>;
34 enable-method = "psci";
35 next-level-cache = <&l2>;
36 operating-points-v2 = <&cpu_opp>;
41 compatible = "operating-points-v2";
45 opp-hz = /bits/ 64 <100000000>;
46 clock-latency-ns = <300>;
49 opp-hz = /bits/ 64 <116667000>;
50 clock-latency-ns = <300>;
53 opp-hz = /bits/ 64 <150000000>;
54 clock-latency-ns = <300>;
57 opp-hz = /bits/ 64 <175000000>;
58 clock-latency-ns = <300>;
61 opp-hz = /bits/ 64 <200000000>;
62 clock-latency-ns = <300>;
65 opp-hz = /bits/ 64 <233334000>;
66 clock-latency-ns = <300>;
69 opp-hz = /bits/ 64 <300000000>;
70 clock-latency-ns = <300>;
73 opp-hz = /bits/ 64 <350000000>;
74 clock-latency-ns = <300>;
77 opp-hz = /bits/ 64 <400000000>;
78 clock-latency-ns = <300>;
81 opp-hz = /bits/ 64 <466667000>;
82 clock-latency-ns = <300>;
85 opp-hz = /bits/ 64 <600000000>;
86 clock-latency-ns = <300>;
89 opp-hz = /bits/ 64 <700000000>;
90 clock-latency-ns = <300>;
93 opp-hz = /bits/ 64 <800000000>;
94 clock-latency-ns = <300>;
97 opp-hz = /bits/ 64 <933334000>;
98 clock-latency-ns = <300>;
101 opp-hz = /bits/ 64 <1200000000>;
102 clock-latency-ns = <300>;
105 opp-hz = /bits/ 64 <1400000000>;
106 clock-latency-ns = <300>;
111 compatible = "arm,psci-0.2";
117 compatible = "fixed-clock";
119 clock-frequency = <20000000>;
122 arm_timer_clk: arm_timer_clk {
124 compatible = "fixed-clock";
125 clock-frequency = <50000000>;
130 compatible = "simple-bus";
131 #address-cells = <1>;
134 interrupt-parent = <&intc>;
137 l2: l2-cache@500c0000 {
138 compatible = "socionext,uniphier-system-cache";
139 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
141 interrupts = <0 190 4>, <0 191 4>;
143 cache-size = <(2 * 1024 * 1024)>;
145 cache-line-size = <128>;
147 next-level-cache = <&l3>;
150 l3: l3-cache@500c8000 {
151 compatible = "socionext,uniphier-system-cache";
152 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
154 interrupts = <0 174 4>, <0 175 4>;
156 cache-size = <(2 * 1024 * 1024)>;
158 cache-line-size = <256>;
162 serial0: serial@54006800 {
163 compatible = "socionext,uniphier-uart";
165 reg = <0x54006800 0x40>;
166 interrupts = <0 33 4>;
167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_uart0>;
169 clocks = <&peri_clk 0>;
170 clock-frequency = <73728000>;
173 serial1: serial@54006900 {
174 compatible = "socionext,uniphier-uart";
176 reg = <0x54006900 0x40>;
177 interrupts = <0 35 4>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_uart1>;
180 clocks = <&peri_clk 1>;
181 clock-frequency = <73728000>;
184 serial2: serial@54006a00 {
185 compatible = "socionext,uniphier-uart";
187 reg = <0x54006a00 0x40>;
188 interrupts = <0 37 4>;
189 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_uart2>;
191 clocks = <&peri_clk 2>;
192 clock-frequency = <73728000>;
195 serial3: serial@54006b00 {
196 compatible = "socionext,uniphier-uart";
198 reg = <0x54006b00 0x40>;
199 interrupts = <0 177 4>;
200 pinctrl-names = "default";
201 pinctrl-0 = <&pinctrl_uart3>;
202 clocks = <&peri_clk 3>;
203 clock-frequency = <73728000>;
206 gpio: gpio@55000000 {
207 compatible = "socionext,uniphier-gpio";
208 reg = <0x55000000 0x200>;
209 interrupt-parent = <&aidet>;
210 interrupt-controller;
211 #interrupt-cells = <2>;
214 gpio-ranges = <&pinctrl 0 0 0>;
215 gpio-ranges-group-names = "gpio_range";
220 compatible = "socionext,uniphier-fi2c";
222 reg = <0x58780000 0x80>;
223 #address-cells = <1>;
225 interrupts = <0 41 4>;
226 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_i2c0>;
228 clocks = <&peri_clk 4>;
229 clock-frequency = <100000>;
233 compatible = "socionext,uniphier-fi2c";
235 reg = <0x58781000 0x80>;
236 #address-cells = <1>;
238 interrupts = <0 42 4>;
239 pinctrl-names = "default";
240 pinctrl-0 = <&pinctrl_i2c1>;
241 clocks = <&peri_clk 5>;
242 clock-frequency = <100000>;
246 compatible = "socionext,uniphier-fi2c";
248 reg = <0x58782000 0x80>;
249 #address-cells = <1>;
251 interrupts = <0 43 4>;
252 pinctrl-names = "default";
253 pinctrl-0 = <&pinctrl_i2c2>;
254 clocks = <&peri_clk 6>;
255 clock-frequency = <100000>;
259 compatible = "socionext,uniphier-fi2c";
261 reg = <0x58783000 0x80>;
262 #address-cells = <1>;
264 interrupts = <0 44 4>;
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_i2c3>;
267 clocks = <&peri_clk 7>;
268 clock-frequency = <100000>;
271 /* i2c4 does not exist */
273 /* chip-internal connection for DMD */
275 compatible = "socionext,uniphier-fi2c";
276 reg = <0x58785000 0x80>;
277 #address-cells = <1>;
279 interrupts = <0 25 4>;
280 clocks = <&peri_clk 9>;
281 clock-frequency = <400000>;
284 /* chip-internal connection for HDMI */
286 compatible = "socionext,uniphier-fi2c";
287 reg = <0x58786000 0x80>;
288 #address-cells = <1>;
290 interrupts = <0 26 4>;
291 clocks = <&peri_clk 10>;
292 clock-frequency = <400000>;
295 system_bus: system-bus@58c00000 {
296 compatible = "socionext,uniphier-system-bus";
298 reg = <0x58c00000 0x400>;
299 #address-cells = <2>;
301 pinctrl-names = "default";
302 pinctrl-0 = <&pinctrl_system_bus>;
306 compatible = "socionext,uniphier-smpctrl";
307 reg = <0x59801000 0x400>;
311 compatible = "socionext,uniphier-pro5-sdctrl",
312 "simple-mfd", "syscon";
313 reg = <0x59810000 0x400>;
317 compatible = "socionext,uniphier-pro5-sd-clock";
322 compatible = "socionext,uniphier-pro5-sd-reset";
328 compatible = "socionext,uniphier-pro5-perictrl",
329 "simple-mfd", "syscon";
330 reg = <0x59820000 0x200>;
333 compatible = "socionext,uniphier-pro5-peri-clock";
338 compatible = "socionext,uniphier-pro5-peri-reset";
344 compatible = "socionext,uniphier-pro5-soc-glue",
345 "simple-mfd", "syscon";
346 reg = <0x5f800000 0x2000>;
350 compatible = "socionext,uniphier-pro5-pinctrl";
355 aidet: aidet@5fc20000 {
356 compatible = "socionext,uniphier-pro5-aidet";
357 reg = <0x5fc20000 0x200>;
358 interrupt-controller;
359 #interrupt-cells = <2>;
363 compatible = "arm,cortex-a9-global-timer";
364 reg = <0x60000200 0x20>;
365 interrupts = <1 11 0x304>;
366 clocks = <&arm_timer_clk>;
370 compatible = "arm,cortex-a9-twd-timer";
371 reg = <0x60000600 0x20>;
372 interrupts = <1 13 0x304>;
373 clocks = <&arm_timer_clk>;
376 intc: interrupt-controller@60001000 {
377 compatible = "arm,cortex-a9-gic";
378 reg = <0x60001000 0x1000>,
380 #interrupt-cells = <3>;
381 interrupt-controller;
385 compatible = "socionext,uniphier-pro5-sysctrl",
386 "simple-mfd", "syscon";
387 reg = <0x61840000 0x10000>;
390 compatible = "socionext,uniphier-pro5-clock";
395 compatible = "socionext,uniphier-pro5-reset";
401 compatible = "socionext,uniphier-pro5-dwc3";
403 reg = <0x65b00000 0x1000>;
404 #address-cells = <1>;
407 pinctrl-names = "default";
408 pinctrl-0 = <&pinctrl_usb0>;
410 compatible = "snps,dwc3";
411 reg = <0x65a00000 0x10000>;
412 interrupts = <0 134 4>;
419 compatible = "socionext,uniphier-pro5-dwc3";
421 reg = <0x65d00000 0x1000>;
422 #address-cells = <1>;
425 pinctrl-names = "default";
426 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
428 compatible = "snps,dwc3";
429 reg = <0x65c00000 0x10000>;
430 interrupts = <0 137 4>;
436 nand: nand@68000000 {
437 compatible = "socionext,uniphier-denali-nand-v5b";
439 reg-names = "nand_data", "denali_reg";
440 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
441 interrupts = <0 65 4>;
442 pinctrl-names = "default";
443 pinctrl-0 = <&pinctrl_nand2cs>;
444 clocks = <&sys_clk 2>;
447 emmc: sdhc@68400000 {
448 compatible = "socionext,uniphier-sdhc";
450 reg = <0x68400000 0x800>;
451 interrupts = <0 78 4>;
452 pinctrl-names = "default";
453 pinctrl-0 = <&pinctrl_emmc>;
454 clocks = <&sd_clk 1>;
455 reset-names = "host";
456 resets = <&sd_rst 1>;
465 compatible = "socionext,uniphier-sdhc";
467 reg = <0x68800000 0x800>;
468 interrupts = <0 76 4>;
469 pinctrl-names = "default", "1.8v";
470 pinctrl-0 = <&pinctrl_sd>;
471 pinctrl-1 = <&pinctrl_sd_1v8>;
472 clocks = <&sd_clk 0>;
473 reset-names = "host";
474 resets = <&sd_rst 0>;
484 #include "uniphier-pinctrl.dtsi"