2 * Device Tree Source for UniPhier Pro5 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
47 compatible = "socionext,uniphier-pro5";
57 compatible = "arm,cortex-a9";
59 clocks = <&sys_clk 32>;
60 enable-method = "psci";
61 next-level-cache = <&l2>;
62 operating-points-v2 = <&cpu_opp>;
67 compatible = "arm,cortex-a9";
69 clocks = <&sys_clk 32>;
70 enable-method = "psci";
71 next-level-cache = <&l2>;
72 operating-points-v2 = <&cpu_opp>;
77 compatible = "operating-points-v2";
81 opp-hz = /bits/ 64 <100000000>;
82 clock-latency-ns = <300>;
85 opp-hz = /bits/ 64 <116667000>;
86 clock-latency-ns = <300>;
89 opp-hz = /bits/ 64 <150000000>;
90 clock-latency-ns = <300>;
93 opp-hz = /bits/ 64 <175000000>;
94 clock-latency-ns = <300>;
97 opp-hz = /bits/ 64 <200000000>;
98 clock-latency-ns = <300>;
101 opp-hz = /bits/ 64 <233334000>;
102 clock-latency-ns = <300>;
105 opp-hz = /bits/ 64 <300000000>;
106 clock-latency-ns = <300>;
109 opp-hz = /bits/ 64 <350000000>;
110 clock-latency-ns = <300>;
113 opp-hz = /bits/ 64 <400000000>;
114 clock-latency-ns = <300>;
117 opp-hz = /bits/ 64 <466667000>;
118 clock-latency-ns = <300>;
121 opp-hz = /bits/ 64 <600000000>;
122 clock-latency-ns = <300>;
125 opp-hz = /bits/ 64 <700000000>;
126 clock-latency-ns = <300>;
129 opp-hz = /bits/ 64 <800000000>;
130 clock-latency-ns = <300>;
133 opp-hz = /bits/ 64 <933334000>;
134 clock-latency-ns = <300>;
137 opp-hz = /bits/ 64 <1200000000>;
138 clock-latency-ns = <300>;
141 opp-hz = /bits/ 64 <1400000000>;
142 clock-latency-ns = <300>;
147 compatible = "arm,psci-0.2";
153 compatible = "fixed-clock";
155 clock-frequency = <20000000>;
158 arm_timer_clk: arm_timer_clk {
160 compatible = "fixed-clock";
161 clock-frequency = <50000000>;
166 compatible = "simple-bus";
167 #address-cells = <1>;
170 interrupt-parent = <&intc>;
173 l2: l2-cache@500c0000 {
174 compatible = "socionext,uniphier-system-cache";
175 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
177 interrupts = <0 190 4>, <0 191 4>;
179 cache-size = <(2 * 1024 * 1024)>;
181 cache-line-size = <128>;
183 next-level-cache = <&l3>;
186 l3: l3-cache@500c8000 {
187 compatible = "socionext,uniphier-system-cache";
188 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
190 interrupts = <0 174 4>, <0 175 4>;
192 cache-size = <(2 * 1024 * 1024)>;
194 cache-line-size = <256>;
198 serial0: serial@54006800 {
199 compatible = "socionext,uniphier-uart";
201 reg = <0x54006800 0x40>;
202 interrupts = <0 33 4>;
203 pinctrl-names = "default";
204 pinctrl-0 = <&pinctrl_uart0>;
205 clocks = <&peri_clk 0>;
206 clock-frequency = <73728000>;
209 serial1: serial@54006900 {
210 compatible = "socionext,uniphier-uart";
212 reg = <0x54006900 0x40>;
213 interrupts = <0 35 4>;
214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_uart1>;
216 clocks = <&peri_clk 1>;
217 clock-frequency = <73728000>;
220 serial2: serial@54006a00 {
221 compatible = "socionext,uniphier-uart";
223 reg = <0x54006a00 0x40>;
224 interrupts = <0 37 4>;
225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_uart2>;
227 clocks = <&peri_clk 2>;
228 clock-frequency = <73728000>;
231 serial3: serial@54006b00 {
232 compatible = "socionext,uniphier-uart";
234 reg = <0x54006b00 0x40>;
235 interrupts = <0 177 4>;
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_uart3>;
238 clocks = <&peri_clk 3>;
239 clock-frequency = <73728000>;
242 port0x: gpio@55000008 {
243 compatible = "socionext,uniphier-gpio";
244 reg = <0x55000008 0x8>;
249 port1x: gpio@55000010 {
250 compatible = "socionext,uniphier-gpio";
251 reg = <0x55000010 0x8>;
256 port2x: gpio@55000018 {
257 compatible = "socionext,uniphier-gpio";
258 reg = <0x55000018 0x8>;
263 port3x: gpio@55000020 {
264 compatible = "socionext,uniphier-gpio";
265 reg = <0x55000020 0x8>;
270 port4: gpio@55000028 {
271 compatible = "socionext,uniphier-gpio";
272 reg = <0x55000028 0x8>;
277 port5x: gpio@55000030 {
278 compatible = "socionext,uniphier-gpio";
279 reg = <0x55000030 0x8>;
284 port6x: gpio@55000038 {
285 compatible = "socionext,uniphier-gpio";
286 reg = <0x55000038 0x8>;
291 port7x: gpio@55000040 {
292 compatible = "socionext,uniphier-gpio";
293 reg = <0x55000040 0x8>;
298 port8x: gpio@55000048 {
299 compatible = "socionext,uniphier-gpio";
300 reg = <0x55000048 0x8>;
305 port9x: gpio@55000050 {
306 compatible = "socionext,uniphier-gpio";
307 reg = <0x55000050 0x8>;
312 port10x: gpio@55000058 {
313 compatible = "socionext,uniphier-gpio";
314 reg = <0x55000058 0x8>;
319 port11x: gpio@55000060 {
320 compatible = "socionext,uniphier-gpio";
321 reg = <0x55000060 0x8>;
326 port12x: gpio@55000068 {
327 compatible = "socionext,uniphier-gpio";
328 reg = <0x55000068 0x8>;
333 port13x: gpio@55000070 {
334 compatible = "socionext,uniphier-gpio";
335 reg = <0x55000070 0x8>;
340 port14x: gpio@55000078 {
341 compatible = "socionext,uniphier-gpio";
342 reg = <0x55000078 0x8>;
347 port17x: gpio@550000a0 {
348 compatible = "socionext,uniphier-gpio";
349 reg = <0x550000a0 0x8>;
354 port18x: gpio@550000a8 {
355 compatible = "socionext,uniphier-gpio";
356 reg = <0x550000a8 0x8>;
361 port19x: gpio@550000b0 {
362 compatible = "socionext,uniphier-gpio";
363 reg = <0x550000b0 0x8>;
368 port20x: gpio@550000b8 {
369 compatible = "socionext,uniphier-gpio";
370 reg = <0x550000b8 0x8>;
375 port21x: gpio@550000c0 {
376 compatible = "socionext,uniphier-gpio";
377 reg = <0x550000c0 0x8>;
382 port22x: gpio@550000c8 {
383 compatible = "socionext,uniphier-gpio";
384 reg = <0x550000c8 0x8>;
389 port23x: gpio@550000d0 {
390 compatible = "socionext,uniphier-gpio";
391 reg = <0x550000d0 0x8>;
396 port24x: gpio@550000d8 {
397 compatible = "socionext,uniphier-gpio";
398 reg = <0x550000d8 0x8>;
403 port25x: gpio@550000e0 {
404 compatible = "socionext,uniphier-gpio";
405 reg = <0x550000e0 0x8>;
410 port26x: gpio@550000e8 {
411 compatible = "socionext,uniphier-gpio";
412 reg = <0x550000e8 0x8>;
417 port27x: gpio@550000f0 {
418 compatible = "socionext,uniphier-gpio";
419 reg = <0x550000f0 0x8>;
424 port28x: gpio@550000f8 {
425 compatible = "socionext,uniphier-gpio";
426 reg = <0x550000f8 0x8>;
431 port29x: gpio@55000100 {
432 compatible = "socionext,uniphier-gpio";
433 reg = <0x55000100 0x8>;
438 port30x: gpio@55000108 {
439 compatible = "socionext,uniphier-gpio";
440 reg = <0x55000108 0x8>;
446 compatible = "socionext,uniphier-fi2c";
448 reg = <0x58780000 0x80>;
449 #address-cells = <1>;
451 interrupts = <0 41 4>;
452 pinctrl-names = "default";
453 pinctrl-0 = <&pinctrl_i2c0>;
454 clocks = <&peri_clk 4>;
455 clock-frequency = <100000>;
459 compatible = "socionext,uniphier-fi2c";
461 reg = <0x58781000 0x80>;
462 #address-cells = <1>;
464 interrupts = <0 42 4>;
465 pinctrl-names = "default";
466 pinctrl-0 = <&pinctrl_i2c1>;
467 clocks = <&peri_clk 5>;
468 clock-frequency = <100000>;
472 compatible = "socionext,uniphier-fi2c";
474 reg = <0x58782000 0x80>;
475 #address-cells = <1>;
477 interrupts = <0 43 4>;
478 pinctrl-names = "default";
479 pinctrl-0 = <&pinctrl_i2c2>;
480 clocks = <&peri_clk 6>;
481 clock-frequency = <100000>;
485 compatible = "socionext,uniphier-fi2c";
487 reg = <0x58783000 0x80>;
488 #address-cells = <1>;
490 interrupts = <0 44 4>;
491 pinctrl-names = "default";
492 pinctrl-0 = <&pinctrl_i2c3>;
493 clocks = <&peri_clk 7>;
494 clock-frequency = <100000>;
497 /* i2c4 does not exist */
499 /* chip-internal connection for DMD */
501 compatible = "socionext,uniphier-fi2c";
502 reg = <0x58785000 0x80>;
503 #address-cells = <1>;
505 interrupts = <0 25 4>;
506 clocks = <&peri_clk 9>;
507 clock-frequency = <400000>;
510 /* chip-internal connection for HDMI */
512 compatible = "socionext,uniphier-fi2c";
513 reg = <0x58786000 0x80>;
514 #address-cells = <1>;
516 interrupts = <0 26 4>;
517 clocks = <&peri_clk 10>;
518 clock-frequency = <400000>;
521 system_bus: system-bus@58c00000 {
522 compatible = "socionext,uniphier-system-bus";
524 reg = <0x58c00000 0x400>;
525 #address-cells = <2>;
527 pinctrl-names = "default";
528 pinctrl-0 = <&pinctrl_system_bus>;
532 compatible = "socionext,uniphier-smpctrl";
533 reg = <0x59801000 0x400>;
537 compatible = "socionext,uniphier-pro5-sdctrl",
538 "simple-mfd", "syscon";
539 reg = <0x59810000 0x800>;
543 compatible = "socionext,uniphier-pro5-sd-clock";
548 compatible = "socionext,uniphier-pro5-sd-reset";
554 compatible = "socionext,uniphier-pro5-perictrl",
555 "simple-mfd", "syscon";
556 reg = <0x59820000 0x200>;
559 compatible = "socionext,uniphier-pro5-peri-clock";
564 compatible = "socionext,uniphier-pro5-peri-reset";
570 compatible = "socionext,uniphier-pro5-soc-glue",
571 "simple-mfd", "syscon";
572 reg = <0x5f800000 0x2000>;
576 compatible = "socionext,uniphier-pro5-pinctrl";
582 compatible = "simple-mfd", "syscon";
583 reg = <0x5fc20000 0x200>;
587 compatible = "arm,cortex-a9-global-timer";
588 reg = <0x60000200 0x20>;
589 interrupts = <1 11 0x304>;
590 clocks = <&arm_timer_clk>;
594 compatible = "arm,cortex-a9-twd-timer";
595 reg = <0x60000600 0x20>;
596 interrupts = <1 13 0x304>;
597 clocks = <&arm_timer_clk>;
600 intc: interrupt-controller@60001000 {
601 compatible = "arm,cortex-a9-gic";
602 reg = <0x60001000 0x1000>,
604 #interrupt-cells = <3>;
605 interrupt-controller;
609 compatible = "socionext,uniphier-pro5-sysctrl",
610 "simple-mfd", "syscon";
611 reg = <0x61840000 0x10000>;
614 compatible = "socionext,uniphier-pro5-clock";
619 compatible = "socionext,uniphier-pro5-reset";
625 compatible = "socionext,uniphier-pro5-dwc3";
627 reg = <0x65b00000 0x1000>;
628 #address-cells = <1>;
631 pinctrl-names = "default";
632 pinctrl-0 = <&pinctrl_usb0>;
634 compatible = "snps,dwc3";
635 reg = <0x65a00000 0x10000>;
636 interrupts = <0 134 4>;
642 compatible = "socionext,uniphier-pro5-dwc3";
644 reg = <0x65d00000 0x1000>;
645 #address-cells = <1>;
648 pinctrl-names = "default";
649 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
651 compatible = "snps,dwc3";
652 reg = <0x65c00000 0x10000>;
653 interrupts = <0 137 4>;
658 nand: nand@68000000 {
659 compatible = "socionext,uniphier-denali-nand-v5b";
661 reg-names = "nand_data", "denali_reg";
662 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
663 interrupts = <0 65 4>;
664 pinctrl-names = "default";
665 pinctrl-0 = <&pinctrl_nand>;
666 clocks = <&sys_clk 2>;
667 nand-ecc-strength = <8>;
670 emmc: sdhc@68400000 {
671 compatible = "socionext,uniphier-sdhc";
673 reg = <0x68400000 0x800>;
674 interrupts = <0 78 4>;
675 pinctrl-names = "default";
676 pinctrl-0 = <&pinctrl_emmc>;
677 clocks = <&sd_clk 1>;
678 reset-names = "host";
679 resets = <&sd_rst 1>;
688 compatible = "socionext,uniphier-sdhc";
690 reg = <0x68800000 0x800>;
691 interrupts = <0 76 4>;
692 pinctrl-names = "default", "1.8v";
693 pinctrl-0 = <&pinctrl_sd>;
694 pinctrl-1 = <&pinctrl_sd_1v8>;
695 clocks = <&sd_clk 0>;
696 reset-names = "host";
697 resets = <&sd_rst 0>;
707 /include/ "uniphier-pinctrl.dtsi"