2 * Device Tree Source for UniPhier Pro4 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 compatible = "socionext,uniphier-pro4";
21 compatible = "arm,cortex-a9";
23 enable-method = "psci";
24 next-level-cache = <&l2>;
29 compatible = "arm,cortex-a9";
31 enable-method = "psci";
32 next-level-cache = <&l2>;
37 compatible = "arm,psci-0.2";
43 compatible = "fixed-clock";
45 clock-frequency = <25000000>;
48 arm_timer_clk: arm_timer_clk {
50 compatible = "fixed-clock";
51 clock-frequency = <50000000>;
56 compatible = "simple-bus";
60 interrupt-parent = <&intc>;
63 l2: l2-cache@500c0000 {
64 compatible = "socionext,uniphier-system-cache";
65 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
67 interrupts = <0 174 4>, <0 175 4>;
69 cache-size = <(768 * 1024)>;
71 cache-line-size = <128>;
75 serial0: serial@54006800 {
76 compatible = "socionext,uniphier-uart";
78 reg = <0x54006800 0x40>;
79 interrupts = <0 33 4>;
80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_uart0>;
82 clocks = <&peri_clk 0>;
83 clock-frequency = <73728000>;
86 serial1: serial@54006900 {
87 compatible = "socionext,uniphier-uart";
89 reg = <0x54006900 0x40>;
90 interrupts = <0 35 4>;
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_uart1>;
93 clocks = <&peri_clk 1>;
94 clock-frequency = <73728000>;
97 serial2: serial@54006a00 {
98 compatible = "socionext,uniphier-uart";
100 reg = <0x54006a00 0x40>;
101 interrupts = <0 37 4>;
102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_uart2>;
104 clocks = <&peri_clk 2>;
105 clock-frequency = <73728000>;
108 serial3: serial@54006b00 {
109 compatible = "socionext,uniphier-uart";
111 reg = <0x54006b00 0x40>;
112 interrupts = <0 177 4>;
113 pinctrl-names = "default";
114 pinctrl-0 = <&pinctrl_uart3>;
115 clocks = <&peri_clk 3>;
116 clock-frequency = <73728000>;
119 gpio: gpio@55000000 {
120 compatible = "socionext,uniphier-gpio";
121 reg = <0x55000000 0x200>;
122 interrupt-parent = <&aidet>;
123 interrupt-controller;
124 #interrupt-cells = <2>;
127 gpio-ranges = <&pinctrl 0 0 0>;
128 gpio-ranges-group-names = "gpio_range";
133 compatible = "socionext,uniphier-fi2c";
135 reg = <0x58780000 0x80>;
136 #address-cells = <1>;
138 interrupts = <0 41 4>;
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_i2c0>;
141 clocks = <&peri_clk 4>;
142 clock-frequency = <100000>;
146 compatible = "socionext,uniphier-fi2c";
148 reg = <0x58781000 0x80>;
149 #address-cells = <1>;
151 interrupts = <0 42 4>;
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_i2c1>;
154 clocks = <&peri_clk 5>;
155 clock-frequency = <100000>;
159 compatible = "socionext,uniphier-fi2c";
161 reg = <0x58782000 0x80>;
162 #address-cells = <1>;
164 interrupts = <0 43 4>;
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_i2c2>;
167 clocks = <&peri_clk 6>;
168 clock-frequency = <100000>;
172 compatible = "socionext,uniphier-fi2c";
174 reg = <0x58783000 0x80>;
175 #address-cells = <1>;
177 interrupts = <0 44 4>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_i2c3>;
180 clocks = <&peri_clk 7>;
181 clock-frequency = <100000>;
184 /* i2c4 does not exist */
186 /* chip-internal connection for DMD */
188 compatible = "socionext,uniphier-fi2c";
189 reg = <0x58785000 0x80>;
190 #address-cells = <1>;
192 interrupts = <0 25 4>;
193 clocks = <&peri_clk 9>;
194 clock-frequency = <400000>;
197 /* chip-internal connection for HDMI */
199 compatible = "socionext,uniphier-fi2c";
200 reg = <0x58786000 0x80>;
201 #address-cells = <1>;
203 interrupts = <0 26 4>;
204 clocks = <&peri_clk 10>;
205 clock-frequency = <400000>;
208 system_bus: system-bus@58c00000 {
209 compatible = "socionext,uniphier-system-bus";
211 reg = <0x58c00000 0x400>;
212 #address-cells = <2>;
214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_system_bus>;
219 compatible = "socionext,uniphier-smpctrl";
220 reg = <0x59801000 0x400>;
224 compatible = "socionext,uniphier-pro4-mioctrl",
225 "simple-mfd", "syscon";
226 reg = <0x59810000 0x800>;
230 compatible = "socionext,uniphier-pro4-mio-clock";
235 compatible = "socionext,uniphier-pro4-mio-reset";
241 compatible = "socionext,uniphier-pro4-perictrl",
242 "simple-mfd", "syscon";
243 reg = <0x59820000 0x200>;
246 compatible = "socionext,uniphier-pro4-peri-clock";
251 compatible = "socionext,uniphier-pro4-peri-reset";
257 compatible = "socionext,uniphier-sdhc";
259 reg = <0x5a400000 0x200>;
260 interrupts = <0 76 4>;
261 pinctrl-names = "default", "1.8v";
262 pinctrl-0 = <&pinctrl_sd>;
263 pinctrl-1 = <&pinctrl_sd_1v8>;
264 clocks = <&mio_clk 0>;
265 reset-names = "host", "bridge";
266 resets = <&mio_rst 0>, <&mio_rst 3>;
274 emmc: sdhc@5a500000 {
275 compatible = "socionext,uniphier-sdhc";
277 reg = <0x5a500000 0x200>;
278 interrupts = <0 78 4>;
279 pinctrl-names = "default", "1.8v";
280 pinctrl-0 = <&pinctrl_emmc>;
281 pinctrl-1 = <&pinctrl_emmc_1v8>;
282 clocks = <&mio_clk 1>;
283 reset-names = "host", "bridge";
284 resets = <&mio_rst 1>, <&mio_rst 4>;
292 compatible = "socionext,uniphier-sdhc";
294 reg = <0x5a600000 0x200>;
295 interrupts = <0 85 4>;
296 pinctrl-names = "default", "1.8v";
297 pinctrl-0 = <&pinctrl_sd1>;
298 pinctrl-1 = <&pinctrl_sd1_1v8>;
299 clocks = <&mio_clk 2>;
300 resets = <&mio_rst 2>, <&mio_rst 5>;
309 compatible = "socionext,uniphier-ehci", "generic-ehci";
311 reg = <0x5a800100 0x100>;
312 interrupts = <0 80 4>;
313 pinctrl-names = "default";
314 pinctrl-0 = <&pinctrl_usb2>;
315 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
316 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
321 compatible = "socionext,uniphier-ehci", "generic-ehci";
323 reg = <0x5a810100 0x100>;
324 interrupts = <0 81 4>;
325 pinctrl-names = "default";
326 pinctrl-0 = <&pinctrl_usb3>;
327 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
328 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
333 compatible = "socionext,uniphier-pro4-soc-glue",
334 "simple-mfd", "syscon";
335 reg = <0x5f800000 0x2000>;
339 compatible = "socionext,uniphier-pro4-pinctrl";
344 aidet: aidet@5fc20000 {
345 compatible = "socionext,uniphier-pro4-aidet";
346 reg = <0x5fc20000 0x200>;
347 interrupt-controller;
348 #interrupt-cells = <2>;
352 compatible = "arm,cortex-a9-global-timer";
353 reg = <0x60000200 0x20>;
354 interrupts = <1 11 0x304>;
355 clocks = <&arm_timer_clk>;
359 compatible = "arm,cortex-a9-twd-timer";
360 reg = <0x60000600 0x20>;
361 interrupts = <1 13 0x304>;
362 clocks = <&arm_timer_clk>;
365 intc: interrupt-controller@60001000 {
366 compatible = "arm,cortex-a9-gic";
367 reg = <0x60001000 0x1000>,
369 #interrupt-cells = <3>;
370 interrupt-controller;
374 compatible = "socionext,uniphier-pro4-sysctrl",
375 "simple-mfd", "syscon";
376 reg = <0x61840000 0x10000>;
379 compatible = "socionext,uniphier-pro4-clock";
384 compatible = "socionext,uniphier-pro4-reset";
390 compatible = "socionext,uniphier-pro4-dwc3";
392 reg = <0x65b00000 0x1000>;
393 #address-cells = <1>;
396 pinctrl-names = "default";
397 pinctrl-0 = <&pinctrl_usb0>;
399 compatible = "snps,dwc3";
400 reg = <0x65a00000 0x10000>;
401 interrupts = <0 134 4>;
408 compatible = "socionext,uniphier-pro4-dwc3";
410 reg = <0x65d00000 0x1000>;
411 #address-cells = <1>;
414 pinctrl-names = "default";
415 pinctrl-0 = <&pinctrl_usb1>;
417 compatible = "snps,dwc3";
418 reg = <0x65c00000 0x10000>;
419 interrupts = <0 137 4>;
425 nand: nand@68000000 {
426 compatible = "socionext,uniphier-denali-nand-v5a";
428 reg-names = "nand_data", "denali_reg";
429 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
430 interrupts = <0 65 4>;
431 pinctrl-names = "default";
432 pinctrl-0 = <&pinctrl_nand>;
433 clocks = <&sys_clk 2>;
438 #include "uniphier-pinctrl.dtsi"