2 * Device Tree Source for UniPhier SoCs default pinctrl settings
4 * Copyright (C) 2015-2017 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 pinctrl_aout: aout_grp {
16 pinctrl_emmc: emmc_grp {
17 groups = "emmc", "emmc_dat8";
21 pinctrl_emmc_1v8: emmc_grp_1v8 {
22 groups = "emmc", "emmc_dat8";
26 pinctrl_ether_mii: ether_mii_grp {
28 function = "ether_mii";
31 pinctrl_ether_rgmii: ether_rgmii_grp {
32 groups = "ether_rgmii";
33 function = "ether_rgmii";
36 pinctrl_ether_rmii: ether_rmii_grp {
37 groups = "ether_rmii";
38 function = "ether_rmii";
41 pinctrl_i2c0: i2c0_grp {
46 pinctrl_i2c1: i2c1_grp {
51 pinctrl_i2c2: i2c2_grp {
56 pinctrl_i2c3: i2c3_grp {
61 pinctrl_i2c4: i2c4_grp {
66 pinctrl_nand: nand_grp {
71 pinctrl_nand2cs: nand2cs_grp {
72 groups = "nand", "nand_cs1";
81 pinctrl_sd_1v8: sd_grp_1v8 {
86 pinctrl_sd1: sd1_grp {
91 pinctrl_sd1_1v8: sd1_grp_1v8 {
96 pinctrl_system_bus: system_bus_grp {
97 groups = "system_bus", "system_bus_cs1";
98 function = "system_bus";
101 pinctrl_uart0: uart0_grp {
106 pinctrl_uart1: uart1_grp {
111 pinctrl_uart2: uart2_grp {
116 pinctrl_uart3: uart3_grp {
121 pinctrl_usb0: usb0_grp {
126 pinctrl_usb1: usb1_grp {
131 pinctrl_usb2: usb2_grp {
136 pinctrl_usb3: usb3_grp {