2 * Device Tree Source for UniPhier PH1-sLD3 SoC
4 * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+ X11
9 /include/ "skeleton.dtsi"
12 compatible = "socionext,ph1-sld3";
17 enable-method = "socionext,uniphier-smp";
21 compatible = "arm,cortex-a9";
27 compatible = "arm,cortex-a9";
35 compatible = "fixed-clock";
36 clock-frequency = <24576000>;
39 arm_timer_clk: arm_timer_clk {
41 compatible = "fixed-clock";
42 clock-frequency = <50000000>;
47 compatible = "fixed-clock";
48 clock-frequency = <36864000>;
51 iobus_clk: iobus_clk {
53 compatible = "fixed-clock";
54 clock-frequency = <100000000>;
59 compatible = "simple-bus";
63 interrupt-parent = <&intc>;
66 compatible = "arm,cortex-a9-global-timer";
67 reg = <0x20000200 0x20>;
68 interrupts = <1 11 0x304>;
69 clocks = <&arm_timer_clk>;
73 compatible = "arm,cortex-a9-twd-timer";
74 reg = <0x20000600 0x20>;
75 interrupts = <1 13 0x304>;
76 clocks = <&arm_timer_clk>;
79 intc: interrupt-controller@20001000 {
80 compatible = "arm,cortex-a9-gic";
81 #interrupt-cells = <3>;
83 reg = <0x20001000 0x1000>,
87 serial0: serial@54006800 {
88 compatible = "socionext,uniphier-uart";
90 reg = <0x54006800 0x40>;
91 interrupts = <0 33 4>;
93 clock-frequency = <36864000>;
96 serial1: serial@54006900 {
97 compatible = "socionext,uniphier-uart";
99 reg = <0x54006900 0x40>;
100 interrupts = <0 35 4>;
101 clocks = <&uart_clk>;
102 clock-frequency = <36864000>;
105 serial2: serial@54006a00 {
106 compatible = "socionext,uniphier-uart";
108 reg = <0x54006a00 0x40>;
109 interrupts = <0 37 4>;
110 clocks = <&uart_clk>;
111 clock-frequency = <36864000>;
115 compatible = "socionext,uniphier-i2c";
117 reg = <0x58400000 0x40>;
118 #address-cells = <1>;
120 interrupts = <0 41 1>;
121 clocks = <&iobus_clk>;
122 clock-frequency = <100000>;
126 compatible = "socionext,uniphier-i2c";
128 reg = <0x58480000 0x40>;
129 #address-cells = <1>;
131 interrupts = <0 42 1>;
132 clocks = <&iobus_clk>;
133 clock-frequency = <100000>;
137 compatible = "socionext,uniphier-i2c";
139 reg = <0x58500000 0x40>;
140 #address-cells = <1>;
142 interrupts = <0 43 1>;
143 clocks = <&iobus_clk>;
144 clock-frequency = <100000>;
148 compatible = "socionext,uniphier-i2c";
150 reg = <0x58580000 0x40>;
151 #address-cells = <1>;
153 interrupts = <0 44 1>;
154 clocks = <&iobus_clk>;
155 clock-frequency = <100000>;
158 /* chip-internal connection for DMD */
160 compatible = "socionext,uniphier-i2c";
161 reg = <0x58600000 0x40>;
162 #address-cells = <1>;
164 interrupts = <0 45 1>;
165 clocks = <&iobus_clk>;
166 clock-frequency = <400000>;
169 system_bus: system-bus@58c00000 {
170 compatible = "socionext,uniphier-system-bus";
171 reg = <0x58c00000 0x400>;
172 #address-cells = <2>;
177 compatible = "socionext,uniphier-smpctrl";
178 reg = <0x59801000 0x400>;
181 mio: mioctrl@59810000 {
182 compatible = "socionext,ph1-sld3-mioctrl";
183 reg = <0x59810000 0x800>;
185 clock-names = "stdmac", "ehci";
186 clocks = <&sysctrl 10>, <&sysctrl 18>;
190 compatible = "socionext,uniphier-ehci", "generic-ehci";
192 reg = <0x5a800100 0x100>;
193 interrupts = <0 80 4>;
194 clocks = <&mio 3>, <&mio 6>;
198 compatible = "socionext,uniphier-ehci", "generic-ehci";
200 reg = <0x5a810100 0x100>;
201 interrupts = <0 81 4>;
202 clocks = <&mio 4>, <&mio 6>;
206 compatible = "socionext,uniphier-ehci", "generic-ehci";
208 reg = <0x5a820100 0x100>;
209 interrupts = <0 82 4>;
210 clocks = <&mio 5>, <&mio 6>;
214 compatible = "socionext,uniphier-ehci", "generic-ehci";
216 reg = <0x5a830100 0x100>;
217 interrupts = <0 83 4>;
218 clocks = <&mio 7>, <&mio 6>;
221 sysctrl: sysctrl@f1840000 {
222 compatible = "socionext,ph1-sld3-sysctrl";
223 reg = <0xf1840000 0x4000>;
229 nand: nand@f8000000 {
230 compatible = "denali,denali-nand-dt";
231 reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
232 reg-names = "nand_data", "denali_reg";