2 * Device Tree Source for UniPhier PH1-sLD3 SoC
4 * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+ X11
9 /include/ "skeleton.dtsi"
12 compatible = "socionext,ph1-sld3";
17 enable-method = "socionext,uniphier-smp";
21 compatible = "arm,cortex-a9";
27 compatible = "arm,cortex-a9";
35 compatible = "fixed-clock";
36 clock-frequency = <24576000>;
39 arm_timer_clk: arm_timer_clk {
41 compatible = "fixed-clock";
42 clock-frequency = <50000000>;
47 compatible = "fixed-clock";
48 clock-frequency = <36864000>;
51 iobus_clk: iobus_clk {
53 compatible = "fixed-clock";
54 clock-frequency = <100000000>;
59 compatible = "simple-bus";
63 interrupt-parent = <&intc>;
66 compatible = "arm,cortex-a9-global-timer";
67 reg = <0x20000200 0x20>;
68 interrupts = <1 11 0x304>;
69 clocks = <&arm_timer_clk>;
73 compatible = "arm,cortex-a9-twd-timer";
74 reg = <0x20000600 0x20>;
75 interrupts = <1 13 0x304>;
76 clocks = <&arm_timer_clk>;
79 intc: interrupt-controller@20001000 {
80 compatible = "arm,cortex-a9-gic";
81 #interrupt-cells = <3>;
83 reg = <0x20001000 0x1000>,
87 serial0: serial@54006800 {
88 compatible = "socionext,uniphier-uart";
90 reg = <0x54006800 0x40>;
91 interrupts = <0 33 4>;
93 clock-frequency = <36864000>;
96 serial1: serial@54006900 {
97 compatible = "socionext,uniphier-uart";
99 reg = <0x54006900 0x40>;
100 interrupts = <0 35 4>;
101 clocks = <&uart_clk>;
102 clock-frequency = <36864000>;
105 serial2: serial@54006a00 {
106 compatible = "socionext,uniphier-uart";
108 reg = <0x54006a00 0x40>;
109 interrupts = <0 37 4>;
110 clocks = <&uart_clk>;
111 clock-frequency = <36864000>;
114 port0x: gpio@55000008 {
115 compatible = "socionext,uniphier-gpio";
116 reg = <0x55000008 0x8>;
121 port1x: gpio@55000010 {
122 compatible = "socionext,uniphier-gpio";
123 reg = <0x55000010 0x8>;
128 port2x: gpio@55000018 {
129 compatible = "socionext,uniphier-gpio";
130 reg = <0x55000018 0x8>;
135 port3x: gpio@55000020 {
136 compatible = "socionext,uniphier-gpio";
137 reg = <0x55000020 0x8>;
142 port4: gpio@55000028 {
143 compatible = "socionext,uniphier-gpio";
144 reg = <0x55000028 0x8>;
149 port5x: gpio@55000030 {
150 compatible = "socionext,uniphier-gpio";
151 reg = <0x55000030 0x8>;
156 port6x: gpio@55000038 {
157 compatible = "socionext,uniphier-gpio";
158 reg = <0x55000038 0x8>;
163 port7x: gpio@55000040 {
164 compatible = "socionext,uniphier-gpio";
165 reg = <0x55000040 0x8>;
170 port8x: gpio@55000048 {
171 compatible = "socionext,uniphier-gpio";
172 reg = <0x55000048 0x8>;
177 port9x: gpio@55000050 {
178 compatible = "socionext,uniphier-gpio";
179 reg = <0x55000050 0x8>;
184 port10x: gpio@55000058 {
185 compatible = "socionext,uniphier-gpio";
186 reg = <0x55000058 0x8>;
191 port11x: gpio@55000060 {
192 compatible = "socionext,uniphier-gpio";
193 reg = <0x55000060 0x8>;
198 port12x: gpio@55000068 {
199 compatible = "socionext,uniphier-gpio";
200 reg = <0x55000068 0x8>;
205 port13x: gpio@55000070 {
206 compatible = "socionext,uniphier-gpio";
207 reg = <0x55000070 0x8>;
212 port14x: gpio@55000078 {
213 compatible = "socionext,uniphier-gpio";
214 reg = <0x55000078 0x8>;
219 port16x: gpio@55000088 {
220 compatible = "socionext,uniphier-gpio";
221 reg = <0x55000088 0x8>;
227 compatible = "socionext,uniphier-i2c";
229 reg = <0x58400000 0x40>;
230 #address-cells = <1>;
232 interrupts = <0 41 1>;
233 clocks = <&iobus_clk>;
234 clock-frequency = <100000>;
238 compatible = "socionext,uniphier-i2c";
240 reg = <0x58480000 0x40>;
241 #address-cells = <1>;
243 interrupts = <0 42 1>;
244 clocks = <&iobus_clk>;
245 clock-frequency = <100000>;
249 compatible = "socionext,uniphier-i2c";
251 reg = <0x58500000 0x40>;
252 #address-cells = <1>;
254 interrupts = <0 43 1>;
255 clocks = <&iobus_clk>;
256 clock-frequency = <100000>;
260 compatible = "socionext,uniphier-i2c";
262 reg = <0x58580000 0x40>;
263 #address-cells = <1>;
265 interrupts = <0 44 1>;
266 clocks = <&iobus_clk>;
267 clock-frequency = <100000>;
270 /* chip-internal connection for DMD */
272 compatible = "socionext,uniphier-i2c";
273 reg = <0x58600000 0x40>;
274 #address-cells = <1>;
276 interrupts = <0 45 1>;
277 clocks = <&iobus_clk>;
278 clock-frequency = <400000>;
281 system_bus: system-bus@58c00000 {
282 compatible = "socionext,uniphier-system-bus";
283 reg = <0x58c00000 0x400>;
284 #address-cells = <2>;
289 compatible = "socionext,uniphier-smpctrl";
290 reg = <0x59801000 0x400>;
293 mio: mioctrl@59810000 {
294 compatible = "socionext,ph1-sld3-mioctrl";
295 reg = <0x59810000 0x800>;
297 clock-names = "stdmac", "ehci";
298 clocks = <&sysctrl 10>, <&sysctrl 18>;
301 emmc: sdhc@5a400000 {
302 compatible = "socionext,uniphier-sdhc";
304 reg = <0x5a400000 0x200>;
305 interrupts = <0 78 4>;
312 compatible = "socionext,uniphier-sdhc";
314 reg = <0x5a500000 0x200>;
315 interrupts = <0 76 4>;
321 compatible = "socionext,uniphier-ehci", "generic-ehci";
323 reg = <0x5a800100 0x100>;
324 interrupts = <0 80 4>;
325 clocks = <&mio 3>, <&mio 6>;
329 compatible = "socionext,uniphier-ehci", "generic-ehci";
331 reg = <0x5a810100 0x100>;
332 interrupts = <0 81 4>;
333 clocks = <&mio 4>, <&mio 6>;
337 compatible = "socionext,uniphier-ehci", "generic-ehci";
339 reg = <0x5a820100 0x100>;
340 interrupts = <0 82 4>;
341 clocks = <&mio 5>, <&mio 6>;
345 compatible = "socionext,uniphier-ehci", "generic-ehci";
347 reg = <0x5a830100 0x100>;
348 interrupts = <0 83 4>;
349 clocks = <&mio 7>, <&mio 6>;
353 compatible = "simple-mfd", "syscon";
354 reg = <0xf1830000 0x200>;
357 sysctrl: sysctrl@f1840000 {
358 compatible = "socionext,ph1-sld3-sysctrl";
359 reg = <0xf1840000 0x4000>;
365 nand: nand@f8000000 {
366 compatible = "denali,denali-nand-dt";
367 reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
368 reg-names = "nand_data", "denali_reg";