arch/arm/dts/uniphier-ph1-sld3.dtsi

   1 /*
   2  * Device Tree Source for UniPhier PH1-sLD3 SoC
   3  *
   4  * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+        X11
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10
  11 / {
  12         compatible = "socionext,ph1-sld3";
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17                 enable-method = "socionext,uniphier-smp";
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                 };
  24
  25                 cpu@1 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a9";
  28                         reg = <1>;
  29                 };
  30         };
  31
  32         clocks {
  33                 refclk: ref {
  34                         #clock-cells = <0>;
  35                         compatible = "fixed-clock";
  36                         clock-frequency = <24576000>;
  37                 };
  38
  39                 arm_timer_clk: arm_timer_clk {
  40                         #clock-cells = <0>;
  41                         compatible = "fixed-clock";
  42                         clock-frequency = <50000000>;
  43                 };
  44
  45                 uart_clk: uart_clk {
  46                         #clock-cells = <0>;
  47                         compatible = "fixed-clock";
  48                         clock-frequency = <36864000>;
  49                 };
  50
  51                 iobus_clk: iobus_clk {
  52                         #clock-cells = <0>;
  53                         compatible = "fixed-clock";
  54                         clock-frequency = <100000000>;
  55                 };
  56         };
  57
  58         soc {
  59                 compatible = "simple-bus";
  60                 #address-cells = <1>;
  61                 #size-cells = <1>;
  62                 ranges;
  63                 interrupt-parent = <&intc>;
  64
  65                 timer@20000200 {
  66                         compatible = "arm,cortex-a9-global-timer";
  67                         reg = <0x20000200 0x20>;
  68                         interrupts = <1 11 0x304>;
  69                         clocks = <&arm_timer_clk>;
  70                 };
  71
  72                 timer@20000600 {
  73                         compatible = "arm,cortex-a9-twd-timer";
  74                         reg = <0x20000600 0x20>;
  75                         interrupts = <1 13 0x304>;
  76                         clocks = <&arm_timer_clk>;
  77                 };
  78
  79                 intc: interrupt-controller@20001000 {
  80                         compatible = "arm,cortex-a9-gic";
  81                         #interrupt-cells = <3>;
  82                         interrupt-controller;
  83                         reg = <0x20001000 0x1000>,
  84                               <0x20000100 0x100>;
  85                 };
  86
  87                 serial0: serial@54006800 {
  88                         compatible = "socionext,uniphier-uart";
  89                         status = "disabled";
  90                         reg = <0x54006800 0x40>;
  91                         interrupts = <0 33 4>;
  92                         clocks = <&uart_clk>;
  93                         clock-frequency = <36864000>;
  94                 };
  95
  96                 serial1: serial@54006900 {
  97                         compatible = "socionext,uniphier-uart";
  98                         status = "disabled";
  99                         reg = <0x54006900 0x40>;
 100                         interrupts = <0 35 4>;
 101                         clocks = <&uart_clk>;
 102                         clock-frequency = <36864000>;
 103                 };
 104
 105                 serial2: serial@54006a00 {
 106                         compatible = "socionext,uniphier-uart";
 107                         status = "disabled";
 108                         reg = <0x54006a00 0x40>;
 109                         interrupts = <0 37 4>;
 110                         clocks = <&uart_clk>;
 111                         clock-frequency = <36864000>;
 112                 };
 113
 114                 port0x: gpio@55000008 {
 115                         compatible = "socionext,uniphier-gpio";
 116                         reg = <0x55000008 0x8>;
 117                         gpio-controller;
 118                         #gpio-cells = <2>;
 119                 };
 120
 121                 port1x: gpio@55000010 {
 122                         compatible = "socionext,uniphier-gpio";
 123                         reg = <0x55000010 0x8>;
 124                         gpio-controller;
 125                         #gpio-cells = <2>;
 126                 };
 127
 128                 port2x: gpio@55000018 {
 129                         compatible = "socionext,uniphier-gpio";
 130                         reg = <0x55000018 0x8>;
 131                         gpio-controller;
 132                         #gpio-cells = <2>;
 133                 };
 134
 135                 port3x: gpio@55000020 {
 136                         compatible = "socionext,uniphier-gpio";
 137                         reg = <0x55000020 0x8>;
 138                         gpio-controller;
 139                         #gpio-cells = <2>;
 140                 };
 141
 142                 port4: gpio@55000028 {
 143                         compatible = "socionext,uniphier-gpio";
 144                         reg = <0x55000028 0x8>;
 145                         gpio-controller;
 146                         #gpio-cells = <2>;
 147                 };
 148
 149                 port5x: gpio@55000030 {
 150                         compatible = "socionext,uniphier-gpio";
 151                         reg = <0x55000030 0x8>;
 152                         gpio-controller;
 153                         #gpio-cells = <2>;
 154                 };
 155
 156                 port6x: gpio@55000038 {
 157                         compatible = "socionext,uniphier-gpio";
 158                         reg = <0x55000038 0x8>;
 159                         gpio-controller;
 160                         #gpio-cells = <2>;
 161                 };
 162
 163                 port7x: gpio@55000040 {
 164                         compatible = "socionext,uniphier-gpio";
 165                         reg = <0x55000040 0x8>;
 166                         gpio-controller;
 167                         #gpio-cells = <2>;
 168                 };
 169
 170                 port8x: gpio@55000048 {
 171                         compatible = "socionext,uniphier-gpio";
 172                         reg = <0x55000048 0x8>;
 173                         gpio-controller;
 174                         #gpio-cells = <2>;
 175                 };
 176
 177                 port9x: gpio@55000050 {
 178                         compatible = "socionext,uniphier-gpio";
 179                         reg = <0x55000050 0x8>;
 180                         gpio-controller;
 181                         #gpio-cells = <2>;
 182                 };
 183
 184                 port10x: gpio@55000058 {
 185                         compatible = "socionext,uniphier-gpio";
 186                         reg = <0x55000058 0x8>;
 187                         gpio-controller;
 188                         #gpio-cells = <2>;
 189                 };
 190
 191                 port11x: gpio@55000060 {
 192                         compatible = "socionext,uniphier-gpio";
 193                         reg = <0x55000060 0x8>;
 194                         gpio-controller;
 195                         #gpio-cells = <2>;
 196                 };
 197
 198                 port12x: gpio@55000068 {
 199                         compatible = "socionext,uniphier-gpio";
 200                         reg = <0x55000068 0x8>;
 201                         gpio-controller;
 202                         #gpio-cells = <2>;
 203                 };
 204
 205                 port13x: gpio@55000070 {
 206                         compatible = "socionext,uniphier-gpio";
 207                         reg = <0x55000070 0x8>;
 208                         gpio-controller;
 209                         #gpio-cells = <2>;
 210                 };
 211
 212                 port14x: gpio@55000078 {
 213                         compatible = "socionext,uniphier-gpio";
 214                         reg = <0x55000078 0x8>;
 215                         gpio-controller;
 216                         #gpio-cells = <2>;
 217                 };
 218
 219                 port16x: gpio@55000088 {
 220                         compatible = "socionext,uniphier-gpio";
 221                         reg = <0x55000088 0x8>;
 222                         gpio-controller;
 223                         #gpio-cells = <2>;
 224                 };
 225
 226                 i2c0: i2c@58400000 {
 227                         compatible = "socionext,uniphier-i2c";
 228                         status = "disabled";
 229                         reg = <0x58400000 0x40>;
 230                         #address-cells = <1>;
 231                         #size-cells = <0>;
 232                         interrupts = <0 41 1>;
 233                         clocks = <&iobus_clk>;
 234                         clock-frequency = <100000>;
 235                 };
 236
 237                 i2c1: i2c@58480000 {
 238                         compatible = "socionext,uniphier-i2c";
 239                         status = "disabled";
 240                         reg = <0x58480000 0x40>;
 241                         #address-cells = <1>;
 242                         #size-cells = <0>;
 243                         interrupts = <0 42 1>;
 244                         clocks = <&iobus_clk>;
 245                         clock-frequency = <100000>;
 246                 };
 247
 248                 i2c2: i2c@58500000 {
 249                         compatible = "socionext,uniphier-i2c";
 250                         status = "disabled";
 251                         reg = <0x58500000 0x40>;
 252                         #address-cells = <1>;
 253                         #size-cells = <0>;
 254                         interrupts = <0 43 1>;
 255                         clocks = <&iobus_clk>;
 256                         clock-frequency = <100000>;
 257                 };
 258
 259                 i2c3: i2c@58580000 {
 260                         compatible = "socionext,uniphier-i2c";
 261                         status = "disabled";
 262                         reg = <0x58580000 0x40>;
 263                         #address-cells = <1>;
 264                         #size-cells = <0>;
 265                         interrupts = <0 44 1>;
 266                         clocks = <&iobus_clk>;
 267                         clock-frequency = <100000>;
 268                 };
 269
 270                 /* chip-internal connection for DMD */
 271                 i2c4: i2c@58600000 {
 272                         compatible = "socionext,uniphier-i2c";
 273                         reg = <0x58600000 0x40>;
 274                         #address-cells = <1>;
 275                         #size-cells = <0>;
 276                         interrupts = <0 45 1>;
 277                         clocks = <&iobus_clk>;
 278                         clock-frequency = <400000>;
 279                 };
 280
 281                 system_bus: system-bus@58c00000 {
 282                         compatible = "socionext,uniphier-system-bus";
 283                         reg = <0x58c00000 0x400>;
 284                         #address-cells = <2>;
 285                         #size-cells = <1>;
 286                 };
 287
 288                 smpctrl@59800000 {
 289                         compatible = "socionext,uniphier-smpctrl";
 290                         reg = <0x59801000 0x400>;
 291                 };
 292
 293                 mio: mioctrl@59810000 {
 294                         compatible = "socionext,ph1-sld3-mioctrl";
 295                         reg = <0x59810000 0x800>;
 296                         #clock-cells = <1>;
 297                         clock-names = "stdmac", "ehci";
 298                         clocks = <&sysctrl 10>, <&sysctrl 18>;
 299                 };
 300
 301                 usb0: usb@5a800100 {
 302                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 303                         status = "disabled";
 304                         reg = <0x5a800100 0x100>;
 305                         interrupts = <0 80 4>;
 306                         clocks = <&mio 3>, <&mio 6>;
 307                 };
 308
 309                 usb1: usb@5a810100 {
 310                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 311                         status = "disabled";
 312                         reg = <0x5a810100 0x100>;
 313                         interrupts = <0 81 4>;
 314                         clocks = <&mio 4>, <&mio 6>;
 315                 };
 316
 317                 usb2: usb@5a820100 {
 318                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 319                         status = "disabled";
 320                         reg = <0x5a820100 0x100>;
 321                         interrupts = <0 82 4>;
 322                         clocks = <&mio 5>, <&mio 6>;
 323                 };
 324
 325                 usb3: usb@5a830100 {
 326                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 327                         status = "disabled";
 328                         reg = <0x5a830100 0x100>;
 329                         interrupts = <0 83 4>;
 330                         clocks = <&mio 7>, <&mio 6>;
 331                 };
 332
 333                 sysctrl: sysctrl@f1840000 {
 334                         compatible = "socionext,ph1-sld3-sysctrl";
 335                         reg = <0xf1840000 0x4000>;
 336                         #clock-cells = <1>;
 337                         clock-names = "ref";
 338                         clocks = <&refclk>;
 339                 };
 340
 341                 nand: nand@f8000000 {
 342                         compatible = "denali,denali-nand-dt";
 343                         reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
 344                         reg-names = "nand_data", "denali_reg";
 345                 };
 346         };
 347 };