arch/arm/dts/uniphier-ph1-pro5.dtsi

   1 /*
   2  * Device Tree Source for UniPhier PH1-Pro5 SoC
   3  *
   4  * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+        X11
   7  */
   8
   9 /include/ "uniphier-common32.dtsi"
  10
  11 / {
  12         compatible = "socionext,ph1-pro5";
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17                 enable-method = "socionext,uniphier-smp";
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                         next-level-cache = <&l2>;
  24                 };
  25
  26                 cpu@1 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a9";
  29                         reg = <1>;
  30                         next-level-cache = <&l2>;
  31                 };
  32         };
  33
  34         clocks {
  35                 arm_timer_clk: arm_timer_clk {
  36                         #clock-cells = <0>;
  37                         compatible = "fixed-clock";
  38                         clock-frequency = <50000000>;
  39                 };
  40
  41                 i2c_clk: i2c_clk {
  42                         #clock-cells = <0>;
  43                         compatible = "fixed-clock";
  44                         clock-frequency = <50000000>;
  45                 };
  46         };
  47 };
  48
  49 &soc {
  50         l2: l2-cache@500c0000 {
  51                 compatible = "socionext,uniphier-system-cache";
  52                 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
  53                 interrupts = <0 190 4>, <0 191 4>;
  54                 cache-unified;
  55                 cache-size = <(2 * 1024 * 1024)>;
  56                 cache-sets = <512>;
  57                 cache-line-size = <128>;
  58                 cache-level = <2>;
  59                 next-level-cache = <&l3>;
  60         };
  61
  62         l3: l3-cache@500c8000 {
  63                 compatible = "socionext,uniphier-system-cache";
  64                 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
  65                 interrupts = <0 174 4>, <0 175 4>;
  66                 cache-unified;
  67                 cache-size = <(2 * 1024 * 1024)>;
  68                 cache-sets = <512>;
  69                 cache-line-size = <256>;
  70                 cache-level = <3>;
  71         };
  72
  73         port0x: gpio@55000008 {
  74                 compatible = "socionext,uniphier-gpio";
  75                 reg = <0x55000008 0x8>;
  76                 gpio-controller;
  77                 #gpio-cells = <2>;
  78         };
  79
  80         port1x: gpio@55000010 {
  81                 compatible = "socionext,uniphier-gpio";
  82                 reg = <0x55000010 0x8>;
  83                 gpio-controller;
  84                 #gpio-cells = <2>;
  85         };
  86
  87         port2x: gpio@55000018 {
  88                 compatible = "socionext,uniphier-gpio";
  89                 reg = <0x55000018 0x8>;
  90                 gpio-controller;
  91                 #gpio-cells = <2>;
  92         };
  93
  94         port3x: gpio@55000020 {
  95                 compatible = "socionext,uniphier-gpio";
  96                 reg = <0x55000020 0x8>;
  97                 gpio-controller;
  98                 #gpio-cells = <2>;
  99         };
 100
 101         port4: gpio@55000028 {
 102                 compatible = "socionext,uniphier-gpio";
 103                 reg = <0x55000028 0x8>;
 104                 gpio-controller;
 105                 #gpio-cells = <2>;
 106         };
 107
 108         port5x: gpio@55000030 {
 109                 compatible = "socionext,uniphier-gpio";
 110                 reg = <0x55000030 0x8>;
 111                 gpio-controller;
 112                 #gpio-cells = <2>;
 113         };
 114
 115         port6x: gpio@55000038 {
 116                 compatible = "socionext,uniphier-gpio";
 117                 reg = <0x55000038 0x8>;
 118                 gpio-controller;
 119                 #gpio-cells = <2>;
 120         };
 121
 122         port7x: gpio@55000040 {
 123                 compatible = "socionext,uniphier-gpio";
 124                 reg = <0x55000040 0x8>;
 125                 gpio-controller;
 126                 #gpio-cells = <2>;
 127         };
 128
 129         port8x: gpio@55000048 {
 130                 compatible = "socionext,uniphier-gpio";
 131                 reg = <0x55000048 0x8>;
 132                 gpio-controller;
 133                 #gpio-cells = <2>;
 134         };
 135
 136         port9x: gpio@55000050 {
 137                 compatible = "socionext,uniphier-gpio";
 138                 reg = <0x55000050 0x8>;
 139                 gpio-controller;
 140                 #gpio-cells = <2>;
 141         };
 142
 143         port10x: gpio@55000058 {
 144                 compatible = "socionext,uniphier-gpio";
 145                 reg = <0x55000058 0x8>;
 146                 gpio-controller;
 147                 #gpio-cells = <2>;
 148         };
 149
 150         port11x: gpio@55000060 {
 151                 compatible = "socionext,uniphier-gpio";
 152                 reg = <0x55000060 0x8>;
 153                 gpio-controller;
 154                 #gpio-cells = <2>;
 155         };
 156
 157         port12x: gpio@55000068 {
 158                 compatible = "socionext,uniphier-gpio";
 159                 reg = <0x55000068 0x8>;
 160                 gpio-controller;
 161                 #gpio-cells = <2>;
 162         };
 163
 164         port13x: gpio@55000070 {
 165                 compatible = "socionext,uniphier-gpio";
 166                 reg = <0x55000070 0x8>;
 167                 gpio-controller;
 168                 #gpio-cells = <2>;
 169         };
 170
 171         port14x: gpio@55000078 {
 172                 compatible = "socionext,uniphier-gpio";
 173                 reg = <0x55000078 0x8>;
 174                 gpio-controller;
 175                 #gpio-cells = <2>;
 176         };
 177
 178         port17x: gpio@550000a0 {
 179                 compatible = "socionext,uniphier-gpio";
 180                 reg = <0x550000a0 0x8>;
 181                 gpio-controller;
 182                 #gpio-cells = <2>;
 183         };
 184
 185         port18x: gpio@550000a8 {
 186                 compatible = "socionext,uniphier-gpio";
 187                 reg = <0x550000a8 0x8>;
 188                 gpio-controller;
 189                 #gpio-cells = <2>;
 190         };
 191
 192         port19x: gpio@550000b0 {
 193                 compatible = "socionext,uniphier-gpio";
 194                 reg = <0x550000b0 0x8>;
 195                 gpio-controller;
 196                 #gpio-cells = <2>;
 197         };
 198
 199         port20x: gpio@550000b8 {
 200                 compatible = "socionext,uniphier-gpio";
 201                 reg = <0x550000b8 0x8>;
 202                 gpio-controller;
 203                 #gpio-cells = <2>;
 204         };
 205
 206         port21x: gpio@550000c0 {
 207                 compatible = "socionext,uniphier-gpio";
 208                 reg = <0x550000c0 0x8>;
 209                 gpio-controller;
 210                 #gpio-cells = <2>;
 211         };
 212
 213         port22x: gpio@550000c8 {
 214                 compatible = "socionext,uniphier-gpio";
 215                 reg = <0x550000c8 0x8>;
 216                 gpio-controller;
 217                 #gpio-cells = <2>;
 218         };
 219
 220         port23x: gpio@550000d0 {
 221                 compatible = "socionext,uniphier-gpio";
 222                 reg = <0x550000d0 0x8>;
 223                 gpio-controller;
 224                 #gpio-cells = <2>;
 225         };
 226
 227         port24x: gpio@550000d8 {
 228                 compatible = "socionext,uniphier-gpio";
 229                 reg = <0x550000d8 0x8>;
 230                 gpio-controller;
 231                 #gpio-cells = <2>;
 232         };
 233
 234         port25x: gpio@550000e0 {
 235                 compatible = "socionext,uniphier-gpio";
 236                 reg = <0x550000e0 0x8>;
 237                 gpio-controller;
 238                 #gpio-cells = <2>;
 239         };
 240
 241         port26x: gpio@550000e8 {
 242                 compatible = "socionext,uniphier-gpio";
 243                 reg = <0x550000e8 0x8>;
 244                 gpio-controller;
 245                 #gpio-cells = <2>;
 246         };
 247
 248         port27x: gpio@550000f0 {
 249                 compatible = "socionext,uniphier-gpio";
 250                 reg = <0x550000f0 0x8>;
 251                 gpio-controller;
 252                 #gpio-cells = <2>;
 253         };
 254
 255         port28x: gpio@550000f8 {
 256                 compatible = "socionext,uniphier-gpio";
 257                 reg = <0x550000f8 0x8>;
 258                 gpio-controller;
 259                 #gpio-cells = <2>;
 260         };
 261
 262         port29x: gpio@55000100 {
 263                 compatible = "socionext,uniphier-gpio";
 264                 reg = <0x55000100 0x8>;
 265                 gpio-controller;
 266                 #gpio-cells = <2>;
 267         };
 268
 269         port30x: gpio@55000108 {
 270                 compatible = "socionext,uniphier-gpio";
 271                 reg = <0x55000108 0x8>;
 272                 gpio-controller;
 273                 #gpio-cells = <2>;
 274         };
 275
 276         i2c0: i2c@58780000 {
 277                 compatible = "socionext,uniphier-fi2c";
 278                 status = "disabled";
 279                 reg = <0x58780000 0x80>;
 280                 #address-cells = <1>;
 281                 #size-cells = <0>;
 282                 interrupts = <0 41 4>;
 283                 pinctrl-names = "default";
 284                 pinctrl-0 = <&pinctrl_i2c0>;
 285                 clocks = <&i2c_clk>;
 286                 clock-frequency = <100000>;
 287         };
 288
 289         i2c1: i2c@58781000 {
 290                 compatible = "socionext,uniphier-fi2c";
 291                 status = "disabled";
 292                 reg = <0x58781000 0x80>;
 293                 #address-cells = <1>;
 294                 #size-cells = <0>;
 295                 interrupts = <0 42 4>;
 296                 pinctrl-names = "default";
 297                 pinctrl-0 = <&pinctrl_i2c1>;
 298                 clocks = <&i2c_clk>;
 299                 clock-frequency = <100000>;
 300         };
 301
 302         i2c2: i2c@58782000 {
 303                 compatible = "socionext,uniphier-fi2c";
 304                 status = "disabled";
 305                 reg = <0x58782000 0x80>;
 306                 #address-cells = <1>;
 307                 #size-cells = <0>;
 308                 interrupts = <0 43 4>;
 309                 pinctrl-names = "default";
 310                 pinctrl-0 = <&pinctrl_i2c2>;
 311                 clocks = <&i2c_clk>;
 312                 clock-frequency = <100000>;
 313         };
 314
 315         i2c3: i2c@58783000 {
 316                 compatible = "socionext,uniphier-fi2c";
 317                 status = "disabled";
 318                 reg = <0x58783000 0x80>;
 319                 #address-cells = <1>;
 320                 #size-cells = <0>;
 321                 interrupts = <0 44 4>;
 322                 pinctrl-names = "default";
 323                 pinctrl-0 = <&pinctrl_i2c3>;
 324                 clocks = <&i2c_clk>;
 325                 clock-frequency = <100000>;
 326         };
 327
 328         /* i2c4 does not exist */
 329
 330         /* chip-internal connection for DMD */
 331         i2c5: i2c@58785000 {
 332                 compatible = "socionext,uniphier-fi2c";
 333                 reg = <0x58785000 0x80>;
 334                 #address-cells = <1>;
 335                 #size-cells = <0>;
 336                 interrupts = <0 25 4>;
 337                 clocks = <&i2c_clk>;
 338                 clock-frequency = <400000>;
 339         };
 340
 341         /* chip-internal connection for HDMI */
 342         i2c6: i2c@58786000 {
 343                 compatible = "socionext,uniphier-fi2c";
 344                 reg = <0x58786000 0x80>;
 345                 #address-cells = <1>;
 346                 #size-cells = <0>;
 347                 interrupts = <0 26 4>;
 348                 clocks = <&i2c_clk>;
 349                 clock-frequency = <400000>;
 350         };
 351
 352         aidet@5fc20000 {
 353                 compatible = "simple-mfd", "syscon";
 354                 reg = <0x5fc20000 0x200>;
 355         };
 356
 357         emmc: sdhc@68400000 {
 358                 compatible = "socionext,uniphier-sdhc";
 359                 status = "disabled";
 360                 reg = <0x68400000 0x800>;
 361                 interrupts = <0 78 4>;
 362                 pinctrl-names = "default";
 363                 pinctrl-0 = <&pinctrl_emmc>;
 364                 clocks = <&mio_clk 1>;
 365                 bus-width = <8>;
 366                 non-removable;
 367         };
 368
 369         sd: sdhc@68800000 {
 370                 compatible = "socionext,uniphier-sdhc";
 371                 status = "disabled";
 372                 reg = <0x68800000 0x800>;
 373                 interrupts = <0 76 4>;
 374                 pinctrl-names = "default", "1.8v";
 375                 pinctrl-0 = <&pinctrl_sd>;
 376                 pinctrl-1 = <&pinctrl_sd_1v8>;
 377                 clocks = <&mio_clk 0>;
 378                 bus-width = <4>;
 379         };
 380
 381         usb0: usb@65a00000 {
 382                 compatible = "socionext,uniphier-xhci", "generic-xhci";
 383                 status = "disabled";
 384                 reg = <0x65a00000 0x100>;
 385                 interrupts = <0 134 4>;
 386                 pinctrl-names = "default";
 387                 pinctrl-0 = <&pinctrl_usb0>;
 388         };
 389
 390         usb1: usb@65c00000 {
 391                 compatible = "socionext,uniphier-xhci", "generic-xhci";
 392                 status = "disabled";
 393                 reg = <0x65c00000 0x100>;
 394                 interrupts = <0 137 4>;
 395                 pinctrl-names = "default";
 396                 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
 397         };
 398 };
 399
 400 &refclk {
 401         clock-frequency = <20000000>;
 402 };
 403
 404 &serial0 {
 405         clock-frequency = <73728000>;
 406 };
 407
 408 &serial1 {
 409         clock-frequency = <73728000>;
 410 };
 411
 412 &serial2 {
 413         clock-frequency = <73728000>;
 414 };
 415
 416 &serial3 {
 417         clock-frequency = <73728000>;
 418 };
 419
 420 &mio_clk {
 421         compatible = "socionext,uniphier-pro5-mio-clock";
 422 };
 423
 424 &mio_rst {
 425         compatible = "socionext,uniphier-pro5-mio-reset";
 426 };
 427
 428 &peri_clk {
 429         compatible = "socionext,uniphier-pro5-peri-clock";
 430 };
 431
 432 &peri_rst {
 433         compatible = "socionext,uniphier-pro5-peri-reset";
 434 };
 435
 436 &pinctrl {
 437         compatible = "socionext,uniphier-pro5-pinctrl";
 438 };
 439
 440 &sys_clk {
 441         compatible = "socionext,uniphier-pro5-clock";
 442 };
 443
 444 &sys_rst {
 445         compatible = "socionext,uniphier-pro5-reset";
 446 };