arch/arm/dts/uniphier-ph1-pro4.dtsi

   1 /*
   2  * Device Tree Source for UniPhier PH1-Pro4 SoC
   3  *
   4  * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+        X11
   7  */
   8
   9 /include/ "uniphier-common32.dtsi"
  10
  11 / {
  12         compatible = "socionext,ph1-pro4";
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17                 enable-method = "socionext,uniphier-smp";
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                         next-level-cache = <&l2>;
  24                 };
  25
  26                 cpu@1 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a9";
  29                         reg = <1>;
  30                         next-level-cache = <&l2>;
  31                 };
  32         };
  33
  34         clocks {
  35                 arm_timer_clk: arm_timer_clk {
  36                         #clock-cells = <0>;
  37                         compatible = "fixed-clock";
  38                         clock-frequency = <50000000>;
  39                 };
  40
  41                 uart_clk: uart_clk {
  42                         #clock-cells = <0>;
  43                         compatible = "fixed-clock";
  44                         clock-frequency = <73728000>;
  45                 };
  46
  47                 i2c_clk: i2c_clk {
  48                         #clock-cells = <0>;
  49                         compatible = "fixed-clock";
  50                         clock-frequency = <50000000>;
  51                 };
  52         };
  53 };
  54
  55 &soc {
  56         l2: l2-cache@500c0000 {
  57                 compatible = "socionext,uniphier-system-cache";
  58                 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
  59                 interrupts = <0 174 4>, <0 175 4>;
  60                 cache-unified;
  61                 cache-size = <(768 * 1024)>;
  62                 cache-sets = <256>;
  63                 cache-line-size = <128>;
  64                 cache-level = <2>;
  65         };
  66
  67         i2c0: i2c@58780000 {
  68                 compatible = "socionext,uniphier-fi2c";
  69                 status = "disabled";
  70                 reg = <0x58780000 0x80>;
  71                 #address-cells = <1>;
  72                 #size-cells = <0>;
  73                 interrupts = <0 41 4>;
  74                 pinctrl-names = "default";
  75                 pinctrl-0 = <&pinctrl_i2c0>;
  76                 clocks = <&i2c_clk>;
  77                 clock-frequency = <100000>;
  78         };
  79
  80         i2c1: i2c@58781000 {
  81                 compatible = "socionext,uniphier-fi2c";
  82                 status = "disabled";
  83                 reg = <0x58781000 0x80>;
  84                 #address-cells = <1>;
  85                 #size-cells = <0>;
  86                 interrupts = <0 42 4>;
  87                 pinctrl-names = "default";
  88                 pinctrl-0 = <&pinctrl_i2c1>;
  89                 clocks = <&i2c_clk>;
  90                 clock-frequency = <100000>;
  91         };
  92
  93         i2c2: i2c@58782000 {
  94                 compatible = "socionext,uniphier-fi2c";
  95                 status = "disabled";
  96                 reg = <0x58782000 0x80>;
  97                 #address-cells = <1>;
  98                 #size-cells = <0>;
  99                 interrupts = <0 43 4>;
 100                 pinctrl-names = "default";
 101                 pinctrl-0 = <&pinctrl_i2c2>;
 102                 clocks = <&i2c_clk>;
 103                 clock-frequency = <100000>;
 104         };
 105
 106         i2c3: i2c@58783000 {
 107                 compatible = "socionext,uniphier-fi2c";
 108                 status = "disabled";
 109                 reg = <0x58783000 0x80>;
 110                 #address-cells = <1>;
 111                 #size-cells = <0>;
 112                 interrupts = <0 44 4>;
 113                 pinctrl-names = "default";
 114                 pinctrl-0 = <&pinctrl_i2c3>;
 115                 clocks = <&i2c_clk>;
 116                 clock-frequency = <100000>;
 117         };
 118
 119         /* i2c4 does not exist */
 120
 121         /* chip-internal connection for DMD */
 122         i2c5: i2c@58785000 {
 123                 compatible = "socionext,uniphier-fi2c";
 124                 reg = <0x58785000 0x80>;
 125                 #address-cells = <1>;
 126                 #size-cells = <0>;
 127                 interrupts = <0 25 4>;
 128                 clocks = <&i2c_clk>;
 129                 clock-frequency = <400000>;
 130         };
 131
 132         /* chip-internal connection for HDMI */
 133         i2c6: i2c@58786000 {
 134                 compatible = "socionext,uniphier-fi2c";
 135                 reg = <0x58786000 0x80>;
 136                 #address-cells = <1>;
 137                 #size-cells = <0>;
 138                 interrupts = <0 26 4>;
 139                 clocks = <&i2c_clk>;
 140                 clock-frequency = <400000>;
 141         };
 142
 143         usb2: usb@5a800100 {
 144                 compatible = "socionext,uniphier-ehci", "generic-ehci";
 145                 status = "disabled";
 146                 reg = <0x5a800100 0x100>;
 147                 interrupts = <0 80 4>;
 148                 pinctrl-names = "default";
 149                 pinctrl-0 = <&pinctrl_usb2>;
 150         };
 151
 152         usb3: usb@5a810100 {
 153                 compatible = "socionext,uniphier-ehci", "generic-ehci";
 154                 status = "disabled";
 155                 reg = <0x5a810100 0x100>;
 156                 interrupts = <0 81 4>;
 157                 pinctrl-names = "default";
 158                 pinctrl-0 = <&pinctrl_usb3>;
 159         };
 160
 161         usb0: usb@65a00000 {
 162                 compatible = "socionext,uniphier-xhci", "generic-xhci";
 163                 status = "disabled";
 164                 reg = <0x65a00000 0x100>;
 165                 interrupts = <0 134 4>;
 166                 pinctrl-names = "default";
 167                 pinctrl-0 = <&pinctrl_usb0>;
 168         };
 169
 170         usb1: usb@65c00000 {
 171                 compatible = "socionext,uniphier-xhci", "generic-xhci";
 172                 status = "disabled";
 173                 reg = <0x65c00000 0x100>;
 174                 interrupts = <0 137 4>;
 175                 pinctrl-names = "default";
 176                 pinctrl-0 = <&pinctrl_usb1>;
 177         };
 178 };
 179
 180 &refclk {
 181         clock-frequency = <25000000>;
 182 };
 183
 184 &serial0 {
 185         clock-frequency = <73728000>;
 186 };
 187
 188 &serial1 {
 189         clock-frequency = <73728000>;
 190 };
 191
 192 &serial2 {
 193         clock-frequency = <73728000>;
 194 };
 195
 196 &serial3 {
 197         clock-frequency = <73728000>;
 198 };
 199
 200 &peri {
 201         compatible = "socionext,ph1-pro4-perictrl";
 202         clock-names = "uart", "fi2c";
 203         clocks = <&sysctrl 3>, <&sysctrl 4>;
 204 };
 205
 206 &pinctrl {
 207         compatible = "socionext,ph1-pro4-pinctrl", "syscon";
 208 };
 209
 210 &sysctrl {
 211         compatible = "socionext,ph1-pro4-sysctrl";
 212 };