2 * Device Tree Source for UniPhier PH1-LD20 SoC
4 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+ X11
9 /memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
12 compatible = "socionext,ph1-ld20";
15 interrupt-parent = <&gic>;
43 compatible = "arm,cortex-a72", "arm,armv8";
45 enable-method = "spin-table";
46 cpu-release-addr = <0 0x80000000>;
51 compatible = "arm,cortex-a72", "arm,armv8";
53 enable-method = "spin-table";
54 cpu-release-addr = <0 0x80000000>;
59 compatible = "arm,cortex-a53", "arm,armv8";
61 enable-method = "spin-table";
62 cpu-release-addr = <0 0x80000000>;
67 compatible = "arm,cortex-a53", "arm,armv8";
69 enable-method = "spin-table";
70 cpu-release-addr = <0 0x80000000>;
76 compatible = "fixed-clock";
78 clock-frequency = <25000000>;
83 compatible = "fixed-clock";
84 clock-frequency = <50000000>;
89 compatible = "arm,armv8-timer";
90 interrupts = <1 13 4>,
97 compatible = "simple-bus";
100 ranges = <0 0 0 0xffffffff>;
103 serial0: serial@54006800 {
104 compatible = "socionext,uniphier-uart";
106 reg = <0x54006800 0x40>;
107 interrupts = <0 33 4>;
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_uart0>;
110 clocks = <&peri_clk 0>;
111 clock-frequency = <58820000>;
114 serial1: serial@54006900 {
115 compatible = "socionext,uniphier-uart";
117 reg = <0x54006900 0x40>;
118 interrupts = <0 35 4>;
119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_uart1>;
121 clocks = <&peri_clk 1>;
122 clock-frequency = <58820000>;
125 serial2: serial@54006a00 {
126 compatible = "socionext,uniphier-uart";
128 reg = <0x54006a00 0x40>;
129 interrupts = <0 37 4>;
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_uart2>;
132 clocks = <&peri_clk 2>;
133 clock-frequency = <58820000>;
136 serial3: serial@54006b00 {
137 compatible = "socionext,uniphier-uart";
139 reg = <0x54006b00 0x40>;
140 interrupts = <0 177 4>;
141 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_uart3>;
143 clocks = <&peri_clk 3>;
144 clock-frequency = <58820000>;
148 compatible = "socionext,uniphier-fi2c";
150 reg = <0x58780000 0x80>;
151 #address-cells = <1>;
153 interrupts = <0 41 4>;
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_i2c0>;
157 clock-frequency = <100000>;
161 compatible = "socionext,uniphier-fi2c";
163 reg = <0x58781000 0x80>;
164 #address-cells = <1>;
166 interrupts = <0 42 4>;
167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_i2c1>;
170 clock-frequency = <100000>;
174 compatible = "socionext,uniphier-fi2c";
175 reg = <0x58782000 0x80>;
176 #address-cells = <1>;
178 interrupts = <0 43 4>;
180 clock-frequency = <400000>;
184 compatible = "socionext,uniphier-fi2c";
186 reg = <0x58783000 0x80>;
187 #address-cells = <1>;
189 interrupts = <0 44 4>;
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_i2c3>;
193 clock-frequency = <100000>;
197 compatible = "socionext,uniphier-fi2c";
199 reg = <0x58784000 0x80>;
200 #address-cells = <1>;
202 interrupts = <0 45 4>;
203 pinctrl-names = "default";
204 pinctrl-0 = <&pinctrl_i2c4>;
206 clock-frequency = <100000>;
210 compatible = "socionext,uniphier-fi2c";
211 reg = <0x58785000 0x80>;
212 #address-cells = <1>;
214 interrupts = <0 25 4>;
216 clock-frequency = <400000>;
219 system_bus: system-bus@58c00000 {
220 compatible = "socionext,uniphier-system-bus";
222 reg = <0x58c00000 0x400>;
223 #address-cells = <2>;
225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_system_bus>;
230 compatible = "socionext,uniphier-smpctrl";
231 reg = <0x59801000 0x400>;
235 compatible = "socionext,uniphier-mioctrl",
236 "simple-mfd", "syscon";
237 reg = <0x59810000 0x800>;
240 compatible = "socionext,uniphier-ld20-mio-clock";
245 compatible = "socionext,uniphier-ld20-mio-reset";
251 compatible = "socionext,uniphier-perictrl",
252 "simple-mfd", "syscon";
253 reg = <0x59820000 0x200>;
256 compatible = "socionext,uniphier-ld20-peri-clock";
261 compatible = "socionext,uniphier-ld20-peri-reset";
267 compatible = "socionext,uniphier-sdhc";
269 reg = <0x5a400000 0x800>;
270 interrupts = <0 76 4>;
271 pinctrl-names = "default";
272 pinctrl-0 = <&pinctrl_sd>;
273 clocks = <&mio_clk 0>;
278 compatible = "socionext,uniphier-soc-glue",
279 "simple-mfd", "syscon";
280 reg = <0x5f800000 0x2000>;
284 compatible = "socionext,uniphier-ld20-pinctrl";
290 compatible = "simple-mfd", "syscon";
291 reg = <0x5fc20000 0x200>;
294 gic: interrupt-controller@5fe00000 {
295 compatible = "arm,gic-v3";
296 reg = <0x5fe00000 0x10000>, /* GICD */
297 <0x5fe80000 0x80000>; /* GICR */
298 interrupt-controller;
299 #interrupt-cells = <3>;
300 interrupts = <1 9 4>;
304 compatible = "socionext,uniphier-sysctrl",
305 "simple-mfd", "syscon";
306 reg = <0x61840000 0x4000>;
309 compatible = "socionext,uniphier-ld20-clock";
314 compatible = "socionext,uniphier-ld20-reset";
321 /include/ "uniphier-pinctrl.dtsi"