arch/arm/dts/uniphier-ld4.dtsi

   1 /*
   2  * Device Tree Source for UniPhier LD4 SoC
   3  *
   4  * Copyright (C) 2015-2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+        X11
   8  */
   9
  10 /include/ "uniphier-common32.dtsi"
  11
  12 / {
  13         compatible = "socionext,uniphier-ld4";
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                         enable-method = "psci";
  24                         next-level-cache = <&l2>;
  25                 };
  26         };
  27
  28         clocks {
  29                 arm_timer_clk: arm_timer_clk {
  30                         #clock-cells = <0>;
  31                         compatible = "fixed-clock";
  32                         clock-frequency = <50000000>;
  33                 };
  34
  35                 iobus_clk: iobus_clk {
  36                         #clock-cells = <0>;
  37                         compatible = "fixed-clock";
  38                         clock-frequency = <100000000>;
  39                 };
  40         };
  41 };
  42
  43 &soc {
  44         l2: l2-cache@500c0000 {
  45                 compatible = "socionext,uniphier-system-cache";
  46                 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
  47                 interrupts = <0 174 4>, <0 175 4>;
  48                 cache-unified;
  49                 cache-size = <(512 * 1024)>;
  50                 cache-sets = <256>;
  51                 cache-line-size = <128>;
  52                 cache-level = <2>;
  53         };
  54
  55         port0x: gpio@55000008 {
  56                 compatible = "socionext,uniphier-gpio";
  57                 reg = <0x55000008 0x8>;
  58                 gpio-controller;
  59                 #gpio-cells = <2>;
  60         };
  61
  62         port1x: gpio@55000010 {
  63                 compatible = "socionext,uniphier-gpio";
  64                 reg = <0x55000010 0x8>;
  65                 gpio-controller;
  66                 #gpio-cells = <2>;
  67         };
  68
  69         port2x: gpio@55000018 {
  70                 compatible = "socionext,uniphier-gpio";
  71                 reg = <0x55000018 0x8>;
  72                 gpio-controller;
  73                 #gpio-cells = <2>;
  74         };
  75
  76         port3x: gpio@55000020 {
  77                 compatible = "socionext,uniphier-gpio";
  78                 reg = <0x55000020 0x8>;
  79                 gpio-controller;
  80                 #gpio-cells = <2>;
  81         };
  82
  83         port4: gpio@55000028 {
  84                 compatible = "socionext,uniphier-gpio";
  85                 reg = <0x55000028 0x8>;
  86                 gpio-controller;
  87                 #gpio-cells = <2>;
  88         };
  89
  90         port5x: gpio@55000030 {
  91                 compatible = "socionext,uniphier-gpio";
  92                 reg = <0x55000030 0x8>;
  93                 gpio-controller;
  94                 #gpio-cells = <2>;
  95         };
  96
  97         port6x: gpio@55000038 {
  98                 compatible = "socionext,uniphier-gpio";
  99                 reg = <0x55000038 0x8>;
 100                 gpio-controller;
 101                 #gpio-cells = <2>;
 102         };
 103
 104         port7x: gpio@55000040 {
 105                 compatible = "socionext,uniphier-gpio";
 106                 reg = <0x55000040 0x8>;
 107                 gpio-controller;
 108                 #gpio-cells = <2>;
 109         };
 110
 111         port8x: gpio@55000048 {
 112                 compatible = "socionext,uniphier-gpio";
 113                 reg = <0x55000048 0x8>;
 114                 gpio-controller;
 115                 #gpio-cells = <2>;
 116         };
 117
 118         port9x: gpio@55000050 {
 119                 compatible = "socionext,uniphier-gpio";
 120                 reg = <0x55000050 0x8>;
 121                 gpio-controller;
 122                 #gpio-cells = <2>;
 123         };
 124
 125         port10x: gpio@55000058 {
 126                 compatible = "socionext,uniphier-gpio";
 127                 reg = <0x55000058 0x8>;
 128                 gpio-controller;
 129                 #gpio-cells = <2>;
 130         };
 131
 132         port11x: gpio@55000060 {
 133                 compatible = "socionext,uniphier-gpio";
 134                 reg = <0x55000060 0x8>;
 135                 gpio-controller;
 136                 #gpio-cells = <2>;
 137         };
 138
 139         port12x: gpio@55000068 {
 140                 compatible = "socionext,uniphier-gpio";
 141                 reg = <0x55000068 0x8>;
 142                 gpio-controller;
 143                 #gpio-cells = <2>;
 144         };
 145
 146         port13x: gpio@55000070 {
 147                 compatible = "socionext,uniphier-gpio";
 148                 reg = <0x55000070 0x8>;
 149                 gpio-controller;
 150                 #gpio-cells = <2>;
 151         };
 152
 153         port14x: gpio@55000078 {
 154                 compatible = "socionext,uniphier-gpio";
 155                 reg = <0x55000078 0x8>;
 156                 gpio-controller;
 157                 #gpio-cells = <2>;
 158         };
 159
 160         port16x: gpio@55000088 {
 161                 compatible = "socionext,uniphier-gpio";
 162                 reg = <0x55000088 0x8>;
 163                 gpio-controller;
 164                 #gpio-cells = <2>;
 165         };
 166
 167         i2c0: i2c@58400000 {
 168                 compatible = "socionext,uniphier-i2c";
 169                 status = "disabled";
 170                 reg = <0x58400000 0x40>;
 171                 #address-cells = <1>;
 172                 #size-cells = <0>;
 173                 interrupts = <0 41 1>;
 174                 pinctrl-names = "default";
 175                 pinctrl-0 = <&pinctrl_i2c0>;
 176                 clocks = <&iobus_clk>;
 177                 clock-frequency = <100000>;
 178         };
 179
 180         i2c1: i2c@58480000 {
 181                 compatible = "socionext,uniphier-i2c";
 182                 status = "disabled";
 183                 reg = <0x58480000 0x40>;
 184                 #address-cells = <1>;
 185                 #size-cells = <0>;
 186                 interrupts = <0 42 1>;
 187                 pinctrl-names = "default";
 188                 pinctrl-0 = <&pinctrl_i2c1>;
 189                 clocks = <&iobus_clk>;
 190                 clock-frequency = <100000>;
 191         };
 192
 193         /* chip-internal connection for DMD */
 194         i2c2: i2c@58500000 {
 195                 compatible = "socionext,uniphier-i2c";
 196                 reg = <0x58500000 0x40>;
 197                 #address-cells = <1>;
 198                 #size-cells = <0>;
 199                 interrupts = <0 43 1>;
 200                 pinctrl-names = "default";
 201                 pinctrl-0 = <&pinctrl_i2c2>;
 202                 clocks = <&iobus_clk>;
 203                 clock-frequency = <400000>;
 204         };
 205
 206         i2c3: i2c@58580000 {
 207                 compatible = "socionext,uniphier-i2c";
 208                 status = "disabled";
 209                 reg = <0x58580000 0x40>;
 210                 #address-cells = <1>;
 211                 #size-cells = <0>;
 212                 interrupts = <0 44 1>;
 213                 pinctrl-names = "default";
 214                 pinctrl-0 = <&pinctrl_i2c3>;
 215                 clocks = <&iobus_clk>;
 216                 clock-frequency = <100000>;
 217         };
 218
 219         sd: sdhc@5a400000 {
 220                 compatible = "socionext,uniphier-sdhc";
 221                 status = "disabled";
 222                 reg = <0x5a400000 0x200>;
 223                 interrupts = <0 76 4>;
 224                 pinctrl-names = "default", "1.8v";
 225                 pinctrl-0 = <&pinctrl_sd>;
 226                 pinctrl-1 = <&pinctrl_sd_1v8>;
 227                 clocks = <&mio_clk 0>;
 228                 reset-names = "host", "bridge";
 229                 resets = <&mio_rst 0>, <&mio_rst 3>;
 230                 bus-width = <4>;
 231         };
 232
 233         emmc: sdhc@5a500000 {
 234                 compatible = "socionext,uniphier-sdhc";
 235                 status = "disabled";
 236                 reg = <0x5a500000 0x200>;
 237                 interrupts = <0 78 4>;
 238                 pinctrl-names = "default", "1.8v";
 239                 pinctrl-0 = <&pinctrl_emmc>;
 240                 pinctrl-1 = <&pinctrl_emmc_1v8>;
 241                 clocks = <&mio_clk 1>;
 242                 reset-names = "host", "bridge", "hw-reset";
 243                 resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
 244                 bus-width = <8>;
 245                 non-removable;
 246         };
 247
 248         usb0: usb@5a800100 {
 249                 compatible = "socionext,uniphier-ehci", "generic-ehci";
 250                 status = "disabled";
 251                 reg = <0x5a800100 0x100>;
 252                 interrupts = <0 80 4>;
 253                 pinctrl-names = "default";
 254                 pinctrl-0 = <&pinctrl_usb0>;
 255                 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
 256                 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 257                          <&mio_rst 12>;
 258         };
 259
 260         usb1: usb@5a810100 {
 261                 compatible = "socionext,uniphier-ehci", "generic-ehci";
 262                 status = "disabled";
 263                 reg = <0x5a810100 0x100>;
 264                 interrupts = <0 81 4>;
 265                 pinctrl-names = "default";
 266                 pinctrl-0 = <&pinctrl_usb1>;
 267                 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
 268                 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 269                          <&mio_rst 13>;
 270         };
 271
 272         usb2: usb@5a820100 {
 273                 compatible = "socionext,uniphier-ehci", "generic-ehci";
 274                 status = "disabled";
 275                 reg = <0x5a820100 0x100>;
 276                 interrupts = <0 82 4>;
 277                 pinctrl-names = "default";
 278                 pinctrl-0 = <&pinctrl_usb2>;
 279                 clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
 280                 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
 281                          <&mio_rst 14>;
 282         };
 283
 284         aidet@61830000 {
 285                 compatible = "simple-mfd", "syscon";
 286                 reg = <0x61830000 0x200>;
 287         };
 288 };
 289
 290 &refclk {
 291         clock-frequency = <24576000>;
 292 };
 293
 294 &serial0 {
 295         clock-frequency = <36864000>;
 296 };
 297
 298 &serial1 {
 299         clock-frequency = <36864000>;
 300 };
 301
 302 &serial2 {
 303         clock-frequency = <36864000>;
 304 };
 305
 306 &serial3 {
 307         interrupts = <0 29 4>;
 308         clock-frequency = <36864000>;
 309 };
 310
 311 &mio_clk {
 312         compatible = "socionext,uniphier-ld4-mio-clock";
 313 };
 314
 315 &mio_rst {
 316         compatible = "socionext,uniphier-ld4-mio-reset";
 317 };
 318
 319 &peri_clk {
 320         compatible = "socionext,uniphier-ld4-peri-clock";
 321 };
 322
 323 &peri_rst {
 324         compatible = "socionext,uniphier-ld4-peri-reset";
 325 };
 326
 327 &pinctrl {
 328         compatible = "socionext,uniphier-ld4-pinctrl";
 329 };
 330
 331 &sys_clk {
 332         compatible = "socionext,uniphier-ld4-clock";
 333 };
 334
 335 &sys_rst {
 336         compatible = "socionext,uniphier-ld4-reset";
 337 };