1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD4 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8 #include <dt-bindings/gpio/uniphier-gpio.h>
11 compatible = "socionext,uniphier-ld4";
21 compatible = "arm,cortex-a9";
23 enable-method = "psci";
24 next-level-cache = <&l2>;
29 compatible = "arm,psci-0.2";
35 compatible = "fixed-clock";
37 clock-frequency = <24576000>;
40 arm_timer_clk: arm-timer {
42 compatible = "fixed-clock";
43 clock-frequency = <50000000>;
48 compatible = "simple-bus";
52 interrupt-parent = <&intc>;
54 l2: l2-cache@500c0000 {
55 compatible = "socionext,uniphier-system-cache";
56 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
58 interrupts = <0 174 4>, <0 175 4>;
60 cache-size = <(512 * 1024)>;
62 cache-line-size = <128>;
66 serial0: serial@54006800 {
67 compatible = "socionext,uniphier-uart";
69 reg = <0x54006800 0x40>;
70 interrupts = <0 33 4>;
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_uart0>;
73 clocks = <&peri_clk 0>;
74 resets = <&peri_rst 0>;
77 serial1: serial@54006900 {
78 compatible = "socionext,uniphier-uart";
80 reg = <0x54006900 0x40>;
81 interrupts = <0 35 4>;
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_uart1>;
84 clocks = <&peri_clk 1>;
85 resets = <&peri_rst 1>;
88 serial2: serial@54006a00 {
89 compatible = "socionext,uniphier-uart";
91 reg = <0x54006a00 0x40>;
92 interrupts = <0 37 4>;
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_uart2>;
95 clocks = <&peri_clk 2>;
96 resets = <&peri_rst 2>;
99 serial3: serial@54006b00 {
100 compatible = "socionext,uniphier-uart";
102 reg = <0x54006b00 0x40>;
103 interrupts = <0 29 4>;
104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_uart3>;
106 clocks = <&peri_clk 3>;
107 resets = <&peri_rst 3>;
110 gpio: gpio@55000000 {
111 compatible = "socionext,uniphier-gpio";
112 reg = <0x55000000 0x200>;
113 interrupt-parent = <&aidet>;
114 interrupt-controller;
115 #interrupt-cells = <2>;
118 gpio-ranges = <&pinctrl 0 0 0>;
119 gpio-ranges-group-names = "gpio_range";
121 socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
125 compatible = "socionext,uniphier-i2c";
127 reg = <0x58400000 0x40>;
128 #address-cells = <1>;
130 interrupts = <0 41 1>;
131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_i2c0>;
133 clocks = <&peri_clk 4>;
134 resets = <&peri_rst 4>;
135 clock-frequency = <100000>;
139 compatible = "socionext,uniphier-i2c";
141 reg = <0x58480000 0x40>;
142 #address-cells = <1>;
144 interrupts = <0 42 1>;
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_i2c1>;
147 clocks = <&peri_clk 5>;
148 resets = <&peri_rst 5>;
149 clock-frequency = <100000>;
152 /* chip-internal connection for DMD */
154 compatible = "socionext,uniphier-i2c";
155 reg = <0x58500000 0x40>;
156 #address-cells = <1>;
158 interrupts = <0 43 1>;
159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_i2c2>;
161 clocks = <&peri_clk 6>;
162 resets = <&peri_rst 6>;
163 clock-frequency = <400000>;
167 compatible = "socionext,uniphier-i2c";
169 reg = <0x58580000 0x40>;
170 #address-cells = <1>;
172 interrupts = <0 44 1>;
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_i2c3>;
175 clocks = <&peri_clk 7>;
176 resets = <&peri_rst 7>;
177 clock-frequency = <100000>;
180 system_bus: system-bus@58c00000 {
181 compatible = "socionext,uniphier-system-bus";
183 reg = <0x58c00000 0x400>;
184 #address-cells = <2>;
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_system_bus>;
191 compatible = "socionext,uniphier-smpctrl";
192 reg = <0x59801000 0x400>;
196 compatible = "socionext,uniphier-ld4-mioctrl",
197 "simple-mfd", "syscon";
198 reg = <0x59810000 0x800>;
201 compatible = "socionext,uniphier-ld4-mio-clock";
206 compatible = "socionext,uniphier-ld4-mio-reset";
212 compatible = "socionext,uniphier-ld4-perictrl",
213 "simple-mfd", "syscon";
214 reg = <0x59820000 0x200>;
217 compatible = "socionext,uniphier-ld4-peri-clock";
222 compatible = "socionext,uniphier-ld4-peri-reset";
228 compatible = "socionext,uniphier-sd-v2.91";
230 reg = <0x5a400000 0x200>;
231 interrupts = <0 76 4>;
232 pinctrl-names = "default", "uhs";
233 pinctrl-0 = <&pinctrl_sd>;
234 pinctrl-1 = <&pinctrl_sd_uhs>;
235 clocks = <&mio_clk 0>;
236 reset-names = "host", "bridge";
237 resets = <&mio_rst 0>, <&mio_rst 3>;
245 emmc: sdhc@5a500000 {
246 compatible = "socionext,uniphier-sd-v2.91";
248 reg = <0x5a500000 0x200>;
249 interrupts = <0 78 4>;
250 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_emmc>;
252 clocks = <&mio_clk 1>;
253 reset-names = "host", "bridge", "hw";
254 resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
262 compatible = "socionext,uniphier-ehci", "generic-ehci";
264 reg = <0x5a800100 0x100>;
265 interrupts = <0 80 4>;
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_usb0>;
268 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
270 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
272 has-transaction-translator;
276 compatible = "socionext,uniphier-ehci", "generic-ehci";
278 reg = <0x5a810100 0x100>;
279 interrupts = <0 81 4>;
280 pinctrl-names = "default";
281 pinctrl-0 = <&pinctrl_usb1>;
282 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
284 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
286 has-transaction-translator;
290 compatible = "socionext,uniphier-ehci", "generic-ehci";
292 reg = <0x5a820100 0x100>;
293 interrupts = <0 82 4>;
294 pinctrl-names = "default";
295 pinctrl-0 = <&pinctrl_usb2>;
296 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
298 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
300 has-transaction-translator;
304 compatible = "socionext,uniphier-ld4-soc-glue",
305 "simple-mfd", "syscon";
306 reg = <0x5f800000 0x2000>;
309 compatible = "socionext,uniphier-ld4-pinctrl";
314 compatible = "socionext,uniphier-ld4-soc-glue-debug",
316 #address-cells = <1>;
318 ranges = <0 0x5f900000 0x2000>;
321 compatible = "socionext,uniphier-efuse";
326 compatible = "socionext,uniphier-efuse";
332 compatible = "arm,cortex-a9-global-timer";
333 reg = <0x60000200 0x20>;
334 interrupts = <1 11 0x104>;
335 clocks = <&arm_timer_clk>;
339 compatible = "arm,cortex-a9-twd-timer";
340 reg = <0x60000600 0x20>;
341 interrupts = <1 13 0x104>;
342 clocks = <&arm_timer_clk>;
345 intc: interrupt-controller@60001000 {
346 compatible = "arm,cortex-a9-gic";
347 reg = <0x60001000 0x1000>,
349 #interrupt-cells = <3>;
350 interrupt-controller;
353 aidet: aidet@61830000 {
354 compatible = "socionext,uniphier-ld4-aidet";
355 reg = <0x61830000 0x200>;
356 interrupt-controller;
357 #interrupt-cells = <2>;
361 compatible = "socionext,uniphier-ld4-sysctrl",
362 "simple-mfd", "syscon";
363 reg = <0x61840000 0x10000>;
366 compatible = "socionext,uniphier-ld4-clock";
371 compatible = "socionext,uniphier-ld4-reset";
376 nand: nand@68000000 {
377 compatible = "socionext,uniphier-denali-nand-v5a";
379 reg-names = "nand_data", "denali_reg";
380 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
381 interrupts = <0 65 4>;
382 pinctrl-names = "default";
383 pinctrl-0 = <&pinctrl_nand2cs>;
384 clocks = <&sys_clk 2>;
385 resets = <&sys_rst 2>;
390 #include "uniphier-pinctrl.dtsi"