2 * Device Tree Source for UniPhier LD4 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 compatible = "socionext,uniphier-ld4";
21 compatible = "arm,cortex-a9";
23 enable-method = "psci";
24 next-level-cache = <&l2>;
29 compatible = "arm,psci-0.2";
35 compatible = "fixed-clock";
37 clock-frequency = <24576000>;
40 arm_timer_clk: arm_timer_clk {
42 compatible = "fixed-clock";
43 clock-frequency = <50000000>;
48 compatible = "simple-bus";
52 interrupt-parent = <&intc>;
55 l2: l2-cache@500c0000 {
56 compatible = "socionext,uniphier-system-cache";
57 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
59 interrupts = <0 174 4>, <0 175 4>;
61 cache-size = <(512 * 1024)>;
63 cache-line-size = <128>;
67 serial0: serial@54006800 {
68 compatible = "socionext,uniphier-uart";
70 reg = <0x54006800 0x40>;
71 interrupts = <0 33 4>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_uart0>;
74 clocks = <&peri_clk 0>;
75 clock-frequency = <36864000>;
78 serial1: serial@54006900 {
79 compatible = "socionext,uniphier-uart";
81 reg = <0x54006900 0x40>;
82 interrupts = <0 35 4>;
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_uart1>;
85 clocks = <&peri_clk 1>;
86 clock-frequency = <36864000>;
89 serial2: serial@54006a00 {
90 compatible = "socionext,uniphier-uart";
92 reg = <0x54006a00 0x40>;
93 interrupts = <0 37 4>;
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_uart2>;
96 clocks = <&peri_clk 2>;
97 clock-frequency = <36864000>;
100 serial3: serial@54006b00 {
101 compatible = "socionext,uniphier-uart";
103 reg = <0x54006b00 0x40>;
104 interrupts = <0 29 4>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_uart3>;
107 clocks = <&peri_clk 3>;
108 clock-frequency = <36864000>;
111 gpio: gpio@55000000 {
112 compatible = "socionext,uniphier-gpio";
113 reg = <0x55000000 0x200>;
114 interrupt-parent = <&aidet>;
115 interrupt-controller;
116 #interrupt-cells = <2>;
119 gpio-ranges = <&pinctrl 0 0 0>;
120 gpio-ranges-group-names = "gpio_range";
125 compatible = "socionext,uniphier-i2c";
127 reg = <0x58400000 0x40>;
128 #address-cells = <1>;
130 interrupts = <0 41 1>;
131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_i2c0>;
133 clocks = <&peri_clk 4>;
134 clock-frequency = <100000>;
138 compatible = "socionext,uniphier-i2c";
140 reg = <0x58480000 0x40>;
141 #address-cells = <1>;
143 interrupts = <0 42 1>;
144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_i2c1>;
146 clocks = <&peri_clk 5>;
147 clock-frequency = <100000>;
150 /* chip-internal connection for DMD */
152 compatible = "socionext,uniphier-i2c";
153 reg = <0x58500000 0x40>;
154 #address-cells = <1>;
156 interrupts = <0 43 1>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_i2c2>;
159 clocks = <&peri_clk 6>;
160 clock-frequency = <400000>;
164 compatible = "socionext,uniphier-i2c";
166 reg = <0x58580000 0x40>;
167 #address-cells = <1>;
169 interrupts = <0 44 1>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_i2c3>;
172 clocks = <&peri_clk 7>;
173 clock-frequency = <100000>;
176 system_bus: system-bus@58c00000 {
177 compatible = "socionext,uniphier-system-bus";
179 reg = <0x58c00000 0x400>;
180 #address-cells = <2>;
182 pinctrl-names = "default";
183 pinctrl-0 = <&pinctrl_system_bus>;
187 compatible = "socionext,uniphier-smpctrl";
188 reg = <0x59801000 0x400>;
192 compatible = "socionext,uniphier-ld4-mioctrl",
193 "simple-mfd", "syscon";
194 reg = <0x59810000 0x800>;
197 compatible = "socionext,uniphier-ld4-mio-clock";
202 compatible = "socionext,uniphier-ld4-mio-reset";
208 compatible = "socionext,uniphier-ld4-perictrl",
209 "simple-mfd", "syscon";
210 reg = <0x59820000 0x200>;
213 compatible = "socionext,uniphier-ld4-peri-clock";
218 compatible = "socionext,uniphier-ld4-peri-reset";
224 compatible = "socionext,uniphier-sdhc";
226 reg = <0x5a400000 0x200>;
227 interrupts = <0 76 4>;
228 pinctrl-names = "default", "1.8v";
229 pinctrl-0 = <&pinctrl_sd>;
230 pinctrl-1 = <&pinctrl_sd_1v8>;
231 clocks = <&mio_clk 0>;
232 reset-names = "host", "bridge";
233 resets = <&mio_rst 0>, <&mio_rst 3>;
241 emmc: sdhc@5a500000 {
242 compatible = "socionext,uniphier-sdhc";
244 reg = <0x5a500000 0x200>;
245 interrupts = <0 78 4>;
246 pinctrl-names = "default", "1.8v";
247 pinctrl-0 = <&pinctrl_emmc>;
248 pinctrl-1 = <&pinctrl_emmc_1v8>;
249 clocks = <&mio_clk 1>;
250 reset-names = "host", "bridge";
251 resets = <&mio_rst 1>, <&mio_rst 4>;
259 compatible = "socionext,uniphier-ehci", "generic-ehci";
261 reg = <0x5a800100 0x100>;
262 interrupts = <0 80 4>;
263 pinctrl-names = "default";
264 pinctrl-0 = <&pinctrl_usb0>;
265 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
266 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
271 compatible = "socionext,uniphier-ehci", "generic-ehci";
273 reg = <0x5a810100 0x100>;
274 interrupts = <0 81 4>;
275 pinctrl-names = "default";
276 pinctrl-0 = <&pinctrl_usb1>;
277 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
278 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
283 compatible = "socionext,uniphier-ehci", "generic-ehci";
285 reg = <0x5a820100 0x100>;
286 interrupts = <0 82 4>;
287 pinctrl-names = "default";
288 pinctrl-0 = <&pinctrl_usb2>;
289 clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
290 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
295 compatible = "socionext,uniphier-ld4-soc-glue",
296 "simple-mfd", "syscon";
297 reg = <0x5f800000 0x2000>;
301 compatible = "socionext,uniphier-ld4-pinctrl";
307 compatible = "arm,cortex-a9-global-timer";
308 reg = <0x60000200 0x20>;
309 interrupts = <1 11 0x104>;
310 clocks = <&arm_timer_clk>;
314 compatible = "arm,cortex-a9-twd-timer";
315 reg = <0x60000600 0x20>;
316 interrupts = <1 13 0x104>;
317 clocks = <&arm_timer_clk>;
320 intc: interrupt-controller@60001000 {
321 compatible = "arm,cortex-a9-gic";
322 reg = <0x60001000 0x1000>,
324 #interrupt-cells = <3>;
325 interrupt-controller;
328 aidet: aidet@61830000 {
329 compatible = "socionext,uniphier-ld4-aidet";
330 reg = <0x61830000 0x200>;
331 interrupt-controller;
332 #interrupt-cells = <2>;
336 compatible = "socionext,uniphier-ld4-sysctrl",
337 "simple-mfd", "syscon";
338 reg = <0x61840000 0x10000>;
341 compatible = "socionext,uniphier-ld4-clock";
346 compatible = "socionext,uniphier-ld4-reset";
351 nand: nand@68000000 {
352 compatible = "socionext,uniphier-denali-nand-v5a";
354 reg-names = "nand_data", "denali_reg";
355 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
356 interrupts = <0 65 4>;
357 pinctrl-names = "default";
358 pinctrl-0 = <&pinctrl_nand2cs>;
359 clocks = <&sys_clk 2>;
364 #include "uniphier-pinctrl.dtsi"