arch/arm/dts/uniphier-ld4.dtsi

   1 /*
   2  * Device Tree Source for UniPhier LD4 SoC
   3  *
   4  * Copyright (C) 2015-2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   8  */
   9
  10 / {
  11         compatible = "socionext,uniphier-ld4";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                         enable-method = "psci";
  24                         next-level-cache = <&l2>;
  25                 };
  26         };
  27
  28         psci {
  29                 compatible = "arm,psci-0.2";
  30                 method = "smc";
  31         };
  32
  33         clocks {
  34                 refclk: ref {
  35                         compatible = "fixed-clock";
  36                         #clock-cells = <0>;
  37                         clock-frequency = <24576000>;
  38                 };
  39
  40                 arm_timer_clk: arm_timer_clk {
  41                         #clock-cells = <0>;
  42                         compatible = "fixed-clock";
  43                         clock-frequency = <50000000>;
  44                 };
  45         };
  46
  47         soc {
  48                 compatible = "simple-bus";
  49                 #address-cells = <1>;
  50                 #size-cells = <1>;
  51                 ranges;
  52                 interrupt-parent = <&intc>;
  53
  54                 l2: l2-cache@500c0000 {
  55                         compatible = "socionext,uniphier-system-cache";
  56                         reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
  57                               <0x506c0000 0x400>;
  58                         interrupts = <0 174 4>, <0 175 4>;
  59                         cache-unified;
  60                         cache-size = <(512 * 1024)>;
  61                         cache-sets = <256>;
  62                         cache-line-size = <128>;
  63                         cache-level = <2>;
  64                 };
  65
  66                 serial0: serial@54006800 {
  67                         compatible = "socionext,uniphier-uart";
  68                         status = "disabled";
  69                         reg = <0x54006800 0x40>;
  70                         interrupts = <0 33 4>;
  71                         pinctrl-names = "default";
  72                         pinctrl-0 = <&pinctrl_uart0>;
  73                         clocks = <&peri_clk 0>;
  74                         clock-frequency = <36864000>;
  75                 };
  76
  77                 serial1: serial@54006900 {
  78                         compatible = "socionext,uniphier-uart";
  79                         status = "disabled";
  80                         reg = <0x54006900 0x40>;
  81                         interrupts = <0 35 4>;
  82                         pinctrl-names = "default";
  83                         pinctrl-0 = <&pinctrl_uart1>;
  84                         clocks = <&peri_clk 1>;
  85                         clock-frequency = <36864000>;
  86                 };
  87
  88                 serial2: serial@54006a00 {
  89                         compatible = "socionext,uniphier-uart";
  90                         status = "disabled";
  91                         reg = <0x54006a00 0x40>;
  92                         interrupts = <0 37 4>;
  93                         pinctrl-names = "default";
  94                         pinctrl-0 = <&pinctrl_uart2>;
  95                         clocks = <&peri_clk 2>;
  96                         clock-frequency = <36864000>;
  97                 };
  98
  99                 serial3: serial@54006b00 {
 100                         compatible = "socionext,uniphier-uart";
 101                         status = "disabled";
 102                         reg = <0x54006b00 0x40>;
 103                         interrupts = <0 29 4>;
 104                         pinctrl-names = "default";
 105                         pinctrl-0 = <&pinctrl_uart3>;
 106                         clocks = <&peri_clk 3>;
 107                         clock-frequency = <36864000>;
 108                 };
 109
 110                 gpio: gpio@55000000 {
 111                         compatible = "socionext,uniphier-gpio";
 112                         reg = <0x55000000 0x200>;
 113                         interrupt-parent = <&aidet>;
 114                         interrupt-controller;
 115                         #interrupt-cells = <2>;
 116                         gpio-controller;
 117                         #gpio-cells = <2>;
 118                         gpio-ranges = <&pinctrl 0 0 0>;
 119                         gpio-ranges-group-names = "gpio_range";
 120                         ngpios = <136>;
 121                 };
 122
 123                 i2c0: i2c@58400000 {
 124                         compatible = "socionext,uniphier-i2c";
 125                         status = "disabled";
 126                         reg = <0x58400000 0x40>;
 127                         #address-cells = <1>;
 128                         #size-cells = <0>;
 129                         interrupts = <0 41 1>;
 130                         pinctrl-names = "default";
 131                         pinctrl-0 = <&pinctrl_i2c0>;
 132                         clocks = <&peri_clk 4>;
 133                         clock-frequency = <100000>;
 134                 };
 135
 136                 i2c1: i2c@58480000 {
 137                         compatible = "socionext,uniphier-i2c";
 138                         status = "disabled";
 139                         reg = <0x58480000 0x40>;
 140                         #address-cells = <1>;
 141                         #size-cells = <0>;
 142                         interrupts = <0 42 1>;
 143                         pinctrl-names = "default";
 144                         pinctrl-0 = <&pinctrl_i2c1>;
 145                         clocks = <&peri_clk 5>;
 146                         clock-frequency = <100000>;
 147                 };
 148
 149                 /* chip-internal connection for DMD */
 150                 i2c2: i2c@58500000 {
 151                         compatible = "socionext,uniphier-i2c";
 152                         reg = <0x58500000 0x40>;
 153                         #address-cells = <1>;
 154                         #size-cells = <0>;
 155                         interrupts = <0 43 1>;
 156                         pinctrl-names = "default";
 157                         pinctrl-0 = <&pinctrl_i2c2>;
 158                         clocks = <&peri_clk 6>;
 159                         clock-frequency = <400000>;
 160                 };
 161
 162                 i2c3: i2c@58580000 {
 163                         compatible = "socionext,uniphier-i2c";
 164                         status = "disabled";
 165                         reg = <0x58580000 0x40>;
 166                         #address-cells = <1>;
 167                         #size-cells = <0>;
 168                         interrupts = <0 44 1>;
 169                         pinctrl-names = "default";
 170                         pinctrl-0 = <&pinctrl_i2c3>;
 171                         clocks = <&peri_clk 7>;
 172                         clock-frequency = <100000>;
 173                 };
 174
 175                 system_bus: system-bus@58c00000 {
 176                         compatible = "socionext,uniphier-system-bus";
 177                         status = "disabled";
 178                         reg = <0x58c00000 0x400>;
 179                         #address-cells = <2>;
 180                         #size-cells = <1>;
 181                         pinctrl-names = "default";
 182                         pinctrl-0 = <&pinctrl_system_bus>;
 183                 };
 184
 185                 smpctrl@59801000 {
 186                         compatible = "socionext,uniphier-smpctrl";
 187                         reg = <0x59801000 0x400>;
 188                 };
 189
 190                 mioctrl@59810000 {
 191                         compatible = "socionext,uniphier-ld4-mioctrl",
 192                                      "simple-mfd", "syscon";
 193                         reg = <0x59810000 0x800>;
 194
 195                         mio_clk: clock {
 196                                 compatible = "socionext,uniphier-ld4-mio-clock";
 197                                 #clock-cells = <1>;
 198                         };
 199
 200                         mio_rst: reset {
 201                                 compatible = "socionext,uniphier-ld4-mio-reset";
 202                                 #reset-cells = <1>;
 203                         };
 204                 };
 205
 206                 perictrl@59820000 {
 207                         compatible = "socionext,uniphier-ld4-perictrl",
 208                                      "simple-mfd", "syscon";
 209                         reg = <0x59820000 0x200>;
 210
 211                         peri_clk: clock {
 212                                 compatible = "socionext,uniphier-ld4-peri-clock";
 213                                 #clock-cells = <1>;
 214                         };
 215
 216                         peri_rst: reset {
 217                                 compatible = "socionext,uniphier-ld4-peri-reset";
 218                                 #reset-cells = <1>;
 219                         };
 220                 };
 221
 222                 sd: sdhc@5a400000 {
 223                         compatible = "socionext,uniphier-sdhc";
 224                         status = "disabled";
 225                         reg = <0x5a400000 0x200>;
 226                         interrupts = <0 76 4>;
 227                         pinctrl-names = "default", "1.8v";
 228                         pinctrl-0 = <&pinctrl_sd>;
 229                         pinctrl-1 = <&pinctrl_sd_1v8>;
 230                         clocks = <&mio_clk 0>;
 231                         reset-names = "host", "bridge";
 232                         resets = <&mio_rst 0>, <&mio_rst 3>;
 233                         bus-width = <4>;
 234                         cap-sd-highspeed;
 235                         sd-uhs-sdr12;
 236                         sd-uhs-sdr25;
 237                         sd-uhs-sdr50;
 238                 };
 239
 240                 emmc: sdhc@5a500000 {
 241                         compatible = "socionext,uniphier-sdhc";
 242                         status = "disabled";
 243                         reg = <0x5a500000 0x200>;
 244                         interrupts = <0 78 4>;
 245                         pinctrl-names = "default", "1.8v";
 246                         pinctrl-0 = <&pinctrl_emmc>;
 247                         pinctrl-1 = <&pinctrl_emmc_1v8>;
 248                         clocks = <&mio_clk 1>;
 249                         reset-names = "host", "bridge";
 250                         resets = <&mio_rst 1>, <&mio_rst 4>;
 251                         bus-width = <8>;
 252                         non-removable;
 253                         cap-mmc-highspeed;
 254                         cap-mmc-hw-reset;
 255                 };
 256
 257                 usb0: usb@5a800100 {
 258                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 259                         status = "disabled";
 260                         reg = <0x5a800100 0x100>;
 261                         interrupts = <0 80 4>;
 262                         pinctrl-names = "default";
 263                         pinctrl-0 = <&pinctrl_usb0>;
 264                         clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
 265                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 266                                  <&mio_rst 12>;
 267                 };
 268
 269                 usb1: usb@5a810100 {
 270                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 271                         status = "disabled";
 272                         reg = <0x5a810100 0x100>;
 273                         interrupts = <0 81 4>;
 274                         pinctrl-names = "default";
 275                         pinctrl-0 = <&pinctrl_usb1>;
 276                         clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
 277                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 278                                  <&mio_rst 13>;
 279                 };
 280
 281                 usb2: usb@5a820100 {
 282                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 283                         status = "disabled";
 284                         reg = <0x5a820100 0x100>;
 285                         interrupts = <0 82 4>;
 286                         pinctrl-names = "default";
 287                         pinctrl-0 = <&pinctrl_usb2>;
 288                         clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
 289                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
 290                                  <&mio_rst 14>;
 291                 };
 292
 293                 soc-glue@5f800000 {
 294                         compatible = "socionext,uniphier-ld4-soc-glue",
 295                                      "simple-mfd", "syscon";
 296                         reg = <0x5f800000 0x2000>;
 297
 298                         pinctrl: pinctrl {
 299                                 compatible = "socionext,uniphier-ld4-pinctrl";
 300                         };
 301                 };
 302
 303                 timer@60000200 {
 304                         compatible = "arm,cortex-a9-global-timer";
 305                         reg = <0x60000200 0x20>;
 306                         interrupts = <1 11 0x104>;
 307                         clocks = <&arm_timer_clk>;
 308                 };
 309
 310                 timer@60000600 {
 311                         compatible = "arm,cortex-a9-twd-timer";
 312                         reg = <0x60000600 0x20>;
 313                         interrupts = <1 13 0x104>;
 314                         clocks = <&arm_timer_clk>;
 315                 };
 316
 317                 intc: interrupt-controller@60001000 {
 318                         compatible = "arm,cortex-a9-gic";
 319                         reg = <0x60001000 0x1000>,
 320                               <0x60000100 0x100>;
 321                         #interrupt-cells = <3>;
 322                         interrupt-controller;
 323                 };
 324
 325                 aidet: aidet@61830000 {
 326                         compatible = "socionext,uniphier-ld4-aidet";
 327                         reg = <0x61830000 0x200>;
 328                         interrupt-controller;
 329                         #interrupt-cells = <2>;
 330                 };
 331
 332                 sysctrl@61840000 {
 333                         compatible = "socionext,uniphier-ld4-sysctrl",
 334                                      "simple-mfd", "syscon";
 335                         reg = <0x61840000 0x10000>;
 336
 337                         sys_clk: clock {
 338                                 compatible = "socionext,uniphier-ld4-clock";
 339                                 #clock-cells = <1>;
 340                         };
 341
 342                         sys_rst: reset {
 343                                 compatible = "socionext,uniphier-ld4-reset";
 344                                 #reset-cells = <1>;
 345                         };
 346                 };
 347
 348                 nand: nand@68000000 {
 349                         compatible = "socionext,uniphier-denali-nand-v5a";
 350                         status = "disabled";
 351                         reg-names = "nand_data", "denali_reg";
 352                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 353                         interrupts = <0 65 4>;
 354                         pinctrl-names = "default";
 355                         pinctrl-0 = <&pinctrl_nand2cs>;
 356                         clocks = <&sys_clk 2>;
 357                 };
 358         };
 359 };
 360
 361 #include "uniphier-pinctrl.dtsi"