1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD20 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/thermal/thermal.h>
12 /memreserve/ 0x80000000 0x02000000;
15 compatible = "socionext,uniphier-ld20";
18 interrupt-parent = <&gic>;
46 compatible = "arm,cortex-a72", "arm,armv8";
48 clocks = <&sys_clk 32>;
49 enable-method = "psci";
50 operating-points-v2 = <&cluster0_opp>;
56 compatible = "arm,cortex-a72", "arm,armv8";
58 clocks = <&sys_clk 32>;
59 enable-method = "psci";
60 operating-points-v2 = <&cluster0_opp>;
66 compatible = "arm,cortex-a53", "arm,armv8";
68 clocks = <&sys_clk 33>;
69 enable-method = "psci";
70 operating-points-v2 = <&cluster1_opp>;
76 compatible = "arm,cortex-a53", "arm,armv8";
78 clocks = <&sys_clk 33>;
79 enable-method = "psci";
80 operating-points-v2 = <&cluster1_opp>;
85 cluster0_opp: opp-table0 {
86 compatible = "operating-points-v2";
90 opp-hz = /bits/ 64 <250000000>;
91 clock-latency-ns = <300>;
94 opp-hz = /bits/ 64 <275000000>;
95 clock-latency-ns = <300>;
98 opp-hz = /bits/ 64 <500000000>;
99 clock-latency-ns = <300>;
102 opp-hz = /bits/ 64 <550000000>;
103 clock-latency-ns = <300>;
106 opp-hz = /bits/ 64 <666667000>;
107 clock-latency-ns = <300>;
110 opp-hz = /bits/ 64 <733334000>;
111 clock-latency-ns = <300>;
114 opp-hz = /bits/ 64 <1000000000>;
115 clock-latency-ns = <300>;
118 opp-hz = /bits/ 64 <1100000000>;
119 clock-latency-ns = <300>;
123 cluster1_opp: opp-table1 {
124 compatible = "operating-points-v2";
128 opp-hz = /bits/ 64 <250000000>;
129 clock-latency-ns = <300>;
132 opp-hz = /bits/ 64 <275000000>;
133 clock-latency-ns = <300>;
136 opp-hz = /bits/ 64 <500000000>;
137 clock-latency-ns = <300>;
140 opp-hz = /bits/ 64 <550000000>;
141 clock-latency-ns = <300>;
144 opp-hz = /bits/ 64 <666667000>;
145 clock-latency-ns = <300>;
148 opp-hz = /bits/ 64 <733334000>;
149 clock-latency-ns = <300>;
152 opp-hz = /bits/ 64 <1000000000>;
153 clock-latency-ns = <300>;
156 opp-hz = /bits/ 64 <1100000000>;
157 clock-latency-ns = <300>;
162 compatible = "arm,psci-1.0";
168 compatible = "fixed-clock";
170 clock-frequency = <25000000>;
174 emmc_pwrseq: emmc-pwrseq {
175 compatible = "mmc-pwrseq-emmc";
176 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
180 compatible = "arm,armv8-timer";
181 interrupts = <1 13 4>,
189 polling-delay-passive = <250>; /* 250ms */
190 polling-delay = <1000>; /* 1000ms */
191 thermal-sensors = <&pvtctl>;
195 temperature = <110000>; /* 110C */
199 cpu_alert: cpu-alert {
200 temperature = <100000>; /* 100C */
209 cooling-device = <&cpu0
210 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
214 cooling-device = <&cpu2
215 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
222 compatible = "simple-bus";
223 #address-cells = <1>;
225 ranges = <0 0 0 0xffffffff>;
227 serial0: serial@54006800 {
228 compatible = "socionext,uniphier-uart";
230 reg = <0x54006800 0x40>;
231 interrupts = <0 33 4>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_uart0>;
234 clocks = <&peri_clk 0>;
235 resets = <&peri_rst 0>;
238 serial1: serial@54006900 {
239 compatible = "socionext,uniphier-uart";
241 reg = <0x54006900 0x40>;
242 interrupts = <0 35 4>;
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_uart1>;
245 clocks = <&peri_clk 1>;
246 resets = <&peri_rst 1>;
249 serial2: serial@54006a00 {
250 compatible = "socionext,uniphier-uart";
252 reg = <0x54006a00 0x40>;
253 interrupts = <0 37 4>;
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_uart2>;
256 clocks = <&peri_clk 2>;
257 resets = <&peri_rst 2>;
260 serial3: serial@54006b00 {
261 compatible = "socionext,uniphier-uart";
263 reg = <0x54006b00 0x40>;
264 interrupts = <0 177 4>;
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_uart3>;
267 clocks = <&peri_clk 3>;
268 resets = <&peri_rst 3>;
271 gpio: gpio@55000000 {
272 compatible = "socionext,uniphier-gpio";
273 reg = <0x55000000 0x200>;
274 interrupt-parent = <&aidet>;
275 interrupt-controller;
276 #interrupt-cells = <2>;
279 gpio-ranges = <&pinctrl 0 0 0>,
282 gpio-ranges-group-names = "gpio_range0",
286 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
291 compatible = "socionext,uniphier-ld20-aio";
292 reg = <0x56000000 0x80000>;
293 interrupts = <0 144 4>;
294 pinctrl-names = "default";
295 pinctrl-0 = <&pinctrl_aout1>,
298 clocks = <&sys_clk 40>;
300 resets = <&sys_rst 40>;
301 #sound-dai-cells = <1>;
302 socionext,syscon = <&soc_glue>;
310 i2s_pcmin2: endpoint {
317 remote-endpoint = <&evea_line>;
322 i2s_hpcmout1: endpoint {
329 remote-endpoint = <&evea_hp>;
333 spdif_port0: port@5 {
334 spdif_hiecout1: endpoint {
339 i2s_epcmout2: endpoint {
344 i2s_epcmout3: endpoint {
348 comp_spdif_port0: port@8 {
349 comp_spdif_hiecout1: endpoint {
355 compatible = "socionext,uniphier-evea";
356 reg = <0x57900000 0x1000>;
357 clock-names = "evea", "exiv";
358 clocks = <&sys_clk 41>, <&sys_clk 42>;
359 reset-names = "evea", "exiv", "adamv";
360 resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
361 #sound-dai-cells = <1>;
364 evea_line: endpoint {
365 remote-endpoint = <&i2s_line>;
371 remote-endpoint = <&i2s_hp>;
377 compatible = "socionext,uniphier-ld20-adamv",
378 "simple-mfd", "syscon";
379 reg = <0x57920000 0x1000>;
382 compatible = "socionext,uniphier-ld20-adamv-reset";
388 compatible = "socionext,uniphier-fi2c";
390 reg = <0x58780000 0x80>;
391 #address-cells = <1>;
393 interrupts = <0 41 4>;
394 pinctrl-names = "default";
395 pinctrl-0 = <&pinctrl_i2c0>;
396 clocks = <&peri_clk 4>;
397 resets = <&peri_rst 4>;
398 clock-frequency = <100000>;
402 compatible = "socionext,uniphier-fi2c";
404 reg = <0x58781000 0x80>;
405 #address-cells = <1>;
407 interrupts = <0 42 4>;
408 pinctrl-names = "default";
409 pinctrl-0 = <&pinctrl_i2c1>;
410 clocks = <&peri_clk 5>;
411 resets = <&peri_rst 5>;
412 clock-frequency = <100000>;
416 compatible = "socionext,uniphier-fi2c";
417 reg = <0x58782000 0x80>;
418 #address-cells = <1>;
420 interrupts = <0 43 4>;
421 clocks = <&peri_clk 6>;
422 resets = <&peri_rst 6>;
423 clock-frequency = <400000>;
427 compatible = "socionext,uniphier-fi2c";
429 reg = <0x58783000 0x80>;
430 #address-cells = <1>;
432 interrupts = <0 44 4>;
433 pinctrl-names = "default";
434 pinctrl-0 = <&pinctrl_i2c3>;
435 clocks = <&peri_clk 7>;
436 resets = <&peri_rst 7>;
437 clock-frequency = <100000>;
441 compatible = "socionext,uniphier-fi2c";
443 reg = <0x58784000 0x80>;
444 #address-cells = <1>;
446 interrupts = <0 45 4>;
447 pinctrl-names = "default";
448 pinctrl-0 = <&pinctrl_i2c4>;
449 clocks = <&peri_clk 8>;
450 resets = <&peri_rst 8>;
451 clock-frequency = <100000>;
455 compatible = "socionext,uniphier-fi2c";
456 reg = <0x58785000 0x80>;
457 #address-cells = <1>;
459 interrupts = <0 25 4>;
460 clocks = <&peri_clk 9>;
461 resets = <&peri_rst 9>;
462 clock-frequency = <400000>;
465 system_bus: system-bus@58c00000 {
466 compatible = "socionext,uniphier-system-bus";
468 reg = <0x58c00000 0x400>;
469 #address-cells = <2>;
471 pinctrl-names = "default";
472 pinctrl-0 = <&pinctrl_system_bus>;
476 compatible = "socionext,uniphier-smpctrl";
477 reg = <0x59801000 0x400>;
481 compatible = "socionext,uniphier-ld20-sdctrl",
482 "simple-mfd", "syscon";
483 reg = <0x59810000 0x400>;
486 compatible = "socionext,uniphier-ld20-sd-clock";
491 compatible = "socionext,uniphier-ld20-sd-reset";
497 compatible = "socionext,uniphier-ld20-perictrl",
498 "simple-mfd", "syscon";
499 reg = <0x59820000 0x200>;
502 compatible = "socionext,uniphier-ld20-peri-clock";
507 compatible = "socionext,uniphier-ld20-peri-reset";
512 emmc: sdhc@5a000000 {
513 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
514 reg = <0x5a000000 0x400>;
515 interrupts = <0 78 4>;
516 pinctrl-names = "default";
517 pinctrl-0 = <&pinctrl_emmc>;
518 clocks = <&sys_clk 4>;
519 resets = <&sys_rst 4>;
523 mmc-pwrseq = <&emmc_pwrseq>;
524 cdns,phy-input-delay-legacy = <9>;
525 cdns,phy-input-delay-mmc-highspeed = <2>;
526 cdns,phy-input-delay-mmc-ddr = <3>;
527 cdns,phy-dll-delay-sdclk = <21>;
528 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
532 compatible = "socionext,uniphier-sd-v3.1.1";
534 reg = <0x5a400000 0x800>;
535 interrupts = <0 76 4>;
536 pinctrl-names = "default";
537 pinctrl-0 = <&pinctrl_sd>;
538 clocks = <&sd_clk 0>;
539 reset-names = "host";
540 resets = <&sd_rst 0>;
545 soc_glue: soc-glue@5f800000 {
546 compatible = "socionext,uniphier-ld20-soc-glue",
547 "simple-mfd", "syscon";
548 reg = <0x5f800000 0x2000>;
551 compatible = "socionext,uniphier-ld20-pinctrl";
556 compatible = "socionext,uniphier-ld20-soc-glue-debug",
558 #address-cells = <1>;
560 ranges = <0 0x5f900000 0x2000>;
563 compatible = "socionext,uniphier-efuse";
568 compatible = "socionext,uniphier-efuse";
573 aidet: aidet@5fc20000 {
574 compatible = "socionext,uniphier-ld20-aidet";
575 reg = <0x5fc20000 0x200>;
576 interrupt-controller;
577 #interrupt-cells = <2>;
580 gic: interrupt-controller@5fe00000 {
581 compatible = "arm,gic-v3";
582 reg = <0x5fe00000 0x10000>, /* GICD */
583 <0x5fe80000 0x80000>; /* GICR */
584 interrupt-controller;
585 #interrupt-cells = <3>;
586 interrupts = <1 9 4>;
590 compatible = "socionext,uniphier-ld20-sysctrl",
591 "simple-mfd", "syscon";
592 reg = <0x61840000 0x10000>;
595 compatible = "socionext,uniphier-ld20-clock";
600 compatible = "socionext,uniphier-ld20-reset";
605 compatible = "socionext,uniphier-wdt";
609 compatible = "socionext,uniphier-ld20-thermal";
610 interrupts = <0 3 4>;
611 #thermal-sensor-cells = <0>;
612 socionext,tmod-calibration = <0x0f22 0x68ee>;
616 eth: ethernet@65000000 {
617 compatible = "socionext,uniphier-ld20-ave4";
619 reg = <0x65000000 0x8500>;
620 interrupts = <0 66 4>;
621 pinctrl-names = "default";
622 pinctrl-0 = <&pinctrl_ether_rgmii>;
623 clock-names = "ether";
624 clocks = <&sys_clk 6>;
625 reset-names = "ether";
626 resets = <&sys_rst 6>;
628 local-mac-address = [00 00 00 00 00 00];
629 socionext,syscon-phy-mode = <&soc_glue 0>;
632 #address-cells = <1>;
638 compatible = "socionext,uniphier-ld20-dwc3";
639 reg = <0x65b00000 0x1000>;
640 #address-cells = <1>;
643 pinctrl-names = "default";
644 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
645 <&pinctrl_usb2>, <&pinctrl_usb3>;
647 compatible = "snps,dwc3";
648 reg = <0x65a00000 0x10000>;
649 interrupts = <0 134 4>;
655 nand: nand@68000000 {
656 compatible = "socionext,uniphier-denali-nand-v5b";
658 reg-names = "nand_data", "denali_reg";
659 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
660 interrupts = <0 65 4>;
661 pinctrl-names = "default";
662 pinctrl-0 = <&pinctrl_nand>;
663 clocks = <&sys_clk 2>;
664 resets = <&sys_rst 2>;
669 #include "uniphier-pinctrl.dtsi"
672 drive-strength = <4>; /* default: 3.5mA */
676 drive-strength = <5>; /* 5mA */
681 drive-strength = <4>; /* default: 3.5mA */
685 drive-strength = <11>; /* 11mA */