2 * Device Tree Source for UniPhier LD20 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 /memreserve/ 0x80000000 0x02000000;
13 compatible = "socionext,uniphier-ld20";
16 interrupt-parent = <&gic>;
44 compatible = "arm,cortex-a72", "arm,armv8";
46 clocks = <&sys_clk 32>;
47 enable-method = "psci";
48 operating-points-v2 = <&cluster0_opp>;
53 compatible = "arm,cortex-a72", "arm,armv8";
55 clocks = <&sys_clk 32>;
56 enable-method = "psci";
57 operating-points-v2 = <&cluster0_opp>;
62 compatible = "arm,cortex-a53", "arm,armv8";
64 clocks = <&sys_clk 33>;
65 enable-method = "psci";
66 operating-points-v2 = <&cluster1_opp>;
71 compatible = "arm,cortex-a53", "arm,armv8";
73 clocks = <&sys_clk 33>;
74 enable-method = "psci";
75 operating-points-v2 = <&cluster1_opp>;
79 cluster0_opp: opp_table0 {
80 compatible = "operating-points-v2";
84 opp-hz = /bits/ 64 <250000000>;
85 clock-latency-ns = <300>;
88 opp-hz = /bits/ 64 <275000000>;
89 clock-latency-ns = <300>;
92 opp-hz = /bits/ 64 <500000000>;
93 clock-latency-ns = <300>;
96 opp-hz = /bits/ 64 <550000000>;
97 clock-latency-ns = <300>;
100 opp-hz = /bits/ 64 <666667000>;
101 clock-latency-ns = <300>;
104 opp-hz = /bits/ 64 <733334000>;
105 clock-latency-ns = <300>;
108 opp-hz = /bits/ 64 <1000000000>;
109 clock-latency-ns = <300>;
112 opp-hz = /bits/ 64 <1100000000>;
113 clock-latency-ns = <300>;
117 cluster1_opp: opp_table1 {
118 compatible = "operating-points-v2";
122 opp-hz = /bits/ 64 <250000000>;
123 clock-latency-ns = <300>;
126 opp-hz = /bits/ 64 <275000000>;
127 clock-latency-ns = <300>;
130 opp-hz = /bits/ 64 <500000000>;
131 clock-latency-ns = <300>;
134 opp-hz = /bits/ 64 <550000000>;
135 clock-latency-ns = <300>;
138 opp-hz = /bits/ 64 <666667000>;
139 clock-latency-ns = <300>;
142 opp-hz = /bits/ 64 <733334000>;
143 clock-latency-ns = <300>;
146 opp-hz = /bits/ 64 <1000000000>;
147 clock-latency-ns = <300>;
150 opp-hz = /bits/ 64 <1100000000>;
151 clock-latency-ns = <300>;
156 compatible = "arm,psci-1.0";
162 compatible = "fixed-clock";
164 clock-frequency = <25000000>;
169 compatible = "arm,armv8-timer";
170 interrupts = <1 13 4>,
177 compatible = "simple-bus";
178 #address-cells = <1>;
180 ranges = <0 0 0 0xffffffff>;
182 serial0: serial@54006800 {
183 compatible = "socionext,uniphier-uart";
185 reg = <0x54006800 0x40>;
186 interrupts = <0 33 4>;
187 pinctrl-names = "default";
188 pinctrl-0 = <&pinctrl_uart0>;
189 clocks = <&peri_clk 0>;
190 clock-frequency = <58820000>;
193 serial1: serial@54006900 {
194 compatible = "socionext,uniphier-uart";
196 reg = <0x54006900 0x40>;
197 interrupts = <0 35 4>;
198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_uart1>;
200 clocks = <&peri_clk 1>;
201 clock-frequency = <58820000>;
204 serial2: serial@54006a00 {
205 compatible = "socionext,uniphier-uart";
207 reg = <0x54006a00 0x40>;
208 interrupts = <0 37 4>;
209 pinctrl-names = "default";
210 pinctrl-0 = <&pinctrl_uart2>;
211 clocks = <&peri_clk 2>;
212 clock-frequency = <58820000>;
215 serial3: serial@54006b00 {
216 compatible = "socionext,uniphier-uart";
218 reg = <0x54006b00 0x40>;
219 interrupts = <0 177 4>;
220 pinctrl-names = "default";
221 pinctrl-0 = <&pinctrl_uart3>;
222 clocks = <&peri_clk 3>;
223 clock-frequency = <58820000>;
226 gpio: gpio@55000000 {
227 compatible = "socionext,uniphier-gpio";
228 reg = <0x55000000 0x200>;
229 interrupt-parent = <&aidet>;
230 interrupt-controller;
231 #interrupt-cells = <2>;
234 gpio-ranges = <&pinctrl 0 0 0>,
237 gpio-ranges-group-names = "gpio_range0",
241 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
246 compatible = "socionext,uniphier-ld20-adamv",
247 "simple-mfd", "syscon";
248 reg = <0x57920000 0x1000>;
251 compatible = "socionext,uniphier-ld20-adamv-reset";
257 compatible = "socionext,uniphier-fi2c";
259 reg = <0x58780000 0x80>;
260 #address-cells = <1>;
262 interrupts = <0 41 4>;
263 pinctrl-names = "default";
264 pinctrl-0 = <&pinctrl_i2c0>;
265 clocks = <&peri_clk 4>;
266 clock-frequency = <100000>;
270 compatible = "socionext,uniphier-fi2c";
272 reg = <0x58781000 0x80>;
273 #address-cells = <1>;
275 interrupts = <0 42 4>;
276 pinctrl-names = "default";
277 pinctrl-0 = <&pinctrl_i2c1>;
278 clocks = <&peri_clk 5>;
279 clock-frequency = <100000>;
283 compatible = "socionext,uniphier-fi2c";
284 reg = <0x58782000 0x80>;
285 #address-cells = <1>;
287 interrupts = <0 43 4>;
288 clocks = <&peri_clk 6>;
289 clock-frequency = <400000>;
293 compatible = "socionext,uniphier-fi2c";
295 reg = <0x58783000 0x80>;
296 #address-cells = <1>;
298 interrupts = <0 44 4>;
299 pinctrl-names = "default";
300 pinctrl-0 = <&pinctrl_i2c3>;
301 clocks = <&peri_clk 7>;
302 clock-frequency = <100000>;
306 compatible = "socionext,uniphier-fi2c";
308 reg = <0x58784000 0x80>;
309 #address-cells = <1>;
311 interrupts = <0 45 4>;
312 pinctrl-names = "default";
313 pinctrl-0 = <&pinctrl_i2c4>;
314 clocks = <&peri_clk 8>;
315 clock-frequency = <100000>;
319 compatible = "socionext,uniphier-fi2c";
320 reg = <0x58785000 0x80>;
321 #address-cells = <1>;
323 interrupts = <0 25 4>;
324 clocks = <&peri_clk 9>;
325 clock-frequency = <400000>;
328 system_bus: system-bus@58c00000 {
329 compatible = "socionext,uniphier-system-bus";
331 reg = <0x58c00000 0x400>;
332 #address-cells = <2>;
334 pinctrl-names = "default";
335 pinctrl-0 = <&pinctrl_system_bus>;
339 compatible = "socionext,uniphier-smpctrl";
340 reg = <0x59801000 0x400>;
344 compatible = "socionext,uniphier-ld20-sdctrl",
345 "simple-mfd", "syscon";
346 reg = <0x59810000 0x400>;
349 compatible = "socionext,uniphier-ld20-sd-clock";
354 compatible = "socionext,uniphier-ld20-sd-reset";
360 compatible = "socionext,uniphier-ld20-perictrl",
361 "simple-mfd", "syscon";
362 reg = <0x59820000 0x200>;
365 compatible = "socionext,uniphier-ld20-peri-clock";
370 compatible = "socionext,uniphier-ld20-peri-reset";
375 emmc: sdhc@5a000000 {
376 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
377 reg = <0x5a000000 0x400>;
378 interrupts = <0 78 4>;
379 pinctrl-names = "default";
380 pinctrl-0 = <&pinctrl_emmc_1v8>;
381 clocks = <&sys_clk 4>;
385 cdns,phy-input-delay-legacy = <4>;
386 cdns,phy-input-delay-mmc-highspeed = <2>;
387 cdns,phy-input-delay-mmc-ddr = <3>;
388 cdns,phy-dll-delay-sdclk = <21>;
389 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
393 compatible = "socionext,uniphier-sdhc";
395 reg = <0x5a400000 0x800>;
396 interrupts = <0 76 4>;
397 pinctrl-names = "default";
398 pinctrl-0 = <&pinctrl_sd>;
399 clocks = <&sd_clk 0>;
400 reset-names = "host";
401 resets = <&sd_rst 0>;
407 compatible = "socionext,uniphier-ld20-soc-glue",
408 "simple-mfd", "syscon";
409 reg = <0x5f800000 0x2000>;
412 compatible = "socionext,uniphier-ld20-pinctrl";
416 aidet: aidet@5fc20000 {
417 compatible = "socionext,uniphier-ld20-aidet";
418 reg = <0x5fc20000 0x200>;
419 interrupt-controller;
420 #interrupt-cells = <2>;
423 gic: interrupt-controller@5fe00000 {
424 compatible = "arm,gic-v3";
425 reg = <0x5fe00000 0x10000>, /* GICD */
426 <0x5fe80000 0x80000>; /* GICR */
427 interrupt-controller;
428 #interrupt-cells = <3>;
429 interrupts = <1 9 4>;
433 compatible = "socionext,uniphier-ld20-sysctrl",
434 "simple-mfd", "syscon";
435 reg = <0x61840000 0x10000>;
438 compatible = "socionext,uniphier-ld20-clock";
443 compatible = "socionext,uniphier-ld20-reset";
448 compatible = "socionext,uniphier-wdt";
453 compatible = "socionext,uniphier-ld20-dwc3";
454 reg = <0x65b00000 0x1000>;
455 #address-cells = <1>;
458 pinctrl-names = "default";
459 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
460 <&pinctrl_usb2>, <&pinctrl_usb3>;
462 compatible = "snps,dwc3";
463 reg = <0x65a00000 0x10000>;
464 interrupts = <0 134 4>;
470 nand: nand@68000000 {
471 compatible = "socionext,uniphier-denali-nand-v5b";
473 reg-names = "nand_data", "denali_reg";
474 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
475 interrupts = <0 65 4>;
476 pinctrl-names = "default";
477 pinctrl-0 = <&pinctrl_nand>;
478 clocks = <&sys_clk 2>;
483 #include "uniphier-pinctrl.dtsi"