2 * Device Tree Source for UniPhier LD20 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: GPL-2.0+ X11
10 /memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
13 compatible = "socionext,uniphier-ld20";
16 interrupt-parent = <&gic>;
44 compatible = "arm,cortex-a72", "arm,armv8";
46 enable-method = "spin-table";
47 cpu-release-addr = <0 0x80000000>;
52 compatible = "arm,cortex-a72", "arm,armv8";
54 enable-method = "spin-table";
55 cpu-release-addr = <0 0x80000000>;
60 compatible = "arm,cortex-a53", "arm,armv8";
62 enable-method = "spin-table";
63 cpu-release-addr = <0 0x80000000>;
68 compatible = "arm,cortex-a53", "arm,armv8";
70 enable-method = "spin-table";
71 cpu-release-addr = <0 0x80000000>;
77 compatible = "fixed-clock";
79 clock-frequency = <25000000>;
84 compatible = "fixed-clock";
85 clock-frequency = <50000000>;
90 compatible = "arm,armv8-timer";
91 interrupts = <1 13 4>,
98 compatible = "simple-bus";
101 ranges = <0 0 0 0xffffffff>;
104 serial0: serial@54006800 {
105 compatible = "socionext,uniphier-uart";
107 reg = <0x54006800 0x40>;
108 interrupts = <0 33 4>;
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_uart0>;
111 clocks = <&peri_clk 0>;
112 clock-frequency = <58820000>;
115 serial1: serial@54006900 {
116 compatible = "socionext,uniphier-uart";
118 reg = <0x54006900 0x40>;
119 interrupts = <0 35 4>;
120 pinctrl-names = "default";
121 pinctrl-0 = <&pinctrl_uart1>;
122 clocks = <&peri_clk 1>;
123 clock-frequency = <58820000>;
126 serial2: serial@54006a00 {
127 compatible = "socionext,uniphier-uart";
129 reg = <0x54006a00 0x40>;
130 interrupts = <0 37 4>;
131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_uart2>;
133 clocks = <&peri_clk 2>;
134 clock-frequency = <58820000>;
137 serial3: serial@54006b00 {
138 compatible = "socionext,uniphier-uart";
140 reg = <0x54006b00 0x40>;
141 interrupts = <0 177 4>;
142 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_uart3>;
144 clocks = <&peri_clk 3>;
145 clock-frequency = <58820000>;
149 compatible = "socionext,uniphier-fi2c";
151 reg = <0x58780000 0x80>;
152 #address-cells = <1>;
154 interrupts = <0 41 4>;
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_i2c0>;
158 clock-frequency = <100000>;
162 compatible = "socionext,uniphier-fi2c";
164 reg = <0x58781000 0x80>;
165 #address-cells = <1>;
167 interrupts = <0 42 4>;
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_i2c1>;
171 clock-frequency = <100000>;
175 compatible = "socionext,uniphier-fi2c";
176 reg = <0x58782000 0x80>;
177 #address-cells = <1>;
179 interrupts = <0 43 4>;
181 clock-frequency = <400000>;
185 compatible = "socionext,uniphier-fi2c";
187 reg = <0x58783000 0x80>;
188 #address-cells = <1>;
190 interrupts = <0 44 4>;
191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_i2c3>;
194 clock-frequency = <100000>;
198 compatible = "socionext,uniphier-fi2c";
200 reg = <0x58784000 0x80>;
201 #address-cells = <1>;
203 interrupts = <0 45 4>;
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_i2c4>;
207 clock-frequency = <100000>;
211 compatible = "socionext,uniphier-fi2c";
212 reg = <0x58785000 0x80>;
213 #address-cells = <1>;
215 interrupts = <0 25 4>;
217 clock-frequency = <400000>;
220 system_bus: system-bus@58c00000 {
221 compatible = "socionext,uniphier-system-bus";
223 reg = <0x58c00000 0x400>;
224 #address-cells = <2>;
226 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_system_bus>;
231 compatible = "socionext,uniphier-smpctrl";
232 reg = <0x59801000 0x400>;
236 compatible = "socionext,uniphier-mioctrl",
237 "simple-mfd", "syscon";
238 reg = <0x59810000 0x800>;
241 compatible = "socionext,uniphier-ld20-mio-clock";
246 compatible = "socionext,uniphier-ld20-mio-reset";
252 compatible = "socionext,uniphier-perictrl",
253 "simple-mfd", "syscon";
254 reg = <0x59820000 0x200>;
257 compatible = "socionext,uniphier-ld20-peri-clock";
262 compatible = "socionext,uniphier-ld20-peri-reset";
268 compatible = "socionext,uniphier-sdhc";
270 reg = <0x5a400000 0x800>;
271 interrupts = <0 76 4>;
272 pinctrl-names = "default";
273 pinctrl-0 = <&pinctrl_sd>;
274 clocks = <&mio_clk 0>;
275 reset-names = "host";
276 resets = <&mio_rst 0>;
281 compatible = "socionext,uniphier-soc-glue",
282 "simple-mfd", "syscon";
283 reg = <0x5f800000 0x2000>;
287 compatible = "socionext,uniphier-ld20-pinctrl";
293 compatible = "simple-mfd", "syscon";
294 reg = <0x5fc20000 0x200>;
297 gic: interrupt-controller@5fe00000 {
298 compatible = "arm,gic-v3";
299 reg = <0x5fe00000 0x10000>, /* GICD */
300 <0x5fe80000 0x80000>; /* GICR */
301 interrupt-controller;
302 #interrupt-cells = <3>;
303 interrupts = <1 9 4>;
307 compatible = "socionext,uniphier-sysctrl",
308 "simple-mfd", "syscon";
309 reg = <0x61840000 0x4000>;
312 compatible = "socionext,uniphier-ld20-clock";
317 compatible = "socionext,uniphier-ld20-reset";
324 /include/ "uniphier-pinctrl.dtsi"