1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD11 SoC
5 // Copyright (C) 2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
11 /memreserve/ 0x80000000 0x02000000;
14 compatible = "socionext,uniphier-ld11";
17 interrupt-parent = <&gic>;
36 compatible = "arm,cortex-a53", "arm,armv8";
38 clocks = <&sys_clk 33>;
39 enable-method = "psci";
40 operating-points-v2 = <&cluster0_opp>;
45 compatible = "arm,cortex-a53", "arm,armv8";
47 clocks = <&sys_clk 33>;
48 enable-method = "psci";
49 operating-points-v2 = <&cluster0_opp>;
53 cluster0_opp: opp-table {
54 compatible = "operating-points-v2";
58 opp-hz = /bits/ 64 <245000000>;
59 clock-latency-ns = <300>;
62 opp-hz = /bits/ 64 <250000000>;
63 clock-latency-ns = <300>;
66 opp-hz = /bits/ 64 <490000000>;
67 clock-latency-ns = <300>;
70 opp-hz = /bits/ 64 <500000000>;
71 clock-latency-ns = <300>;
74 opp-hz = /bits/ 64 <653334000>;
75 clock-latency-ns = <300>;
78 opp-hz = /bits/ 64 <666667000>;
79 clock-latency-ns = <300>;
82 opp-hz = /bits/ 64 <980000000>;
83 clock-latency-ns = <300>;
88 compatible = "arm,psci-1.0";
94 compatible = "fixed-clock";
96 clock-frequency = <25000000>;
100 emmc_pwrseq: emmc-pwrseq {
101 compatible = "mmc-pwrseq-emmc";
102 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
106 compatible = "arm,armv8-timer";
107 interrupts = <1 13 4>,
114 compatible = "simple-bus";
115 #address-cells = <1>;
117 ranges = <0 0 0 0xffffffff>;
119 serial0: serial@54006800 {
120 compatible = "socionext,uniphier-uart";
122 reg = <0x54006800 0x40>;
123 interrupts = <0 33 4>;
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_uart0>;
126 clocks = <&peri_clk 0>;
127 clock-frequency = <58820000>;
128 resets = <&peri_rst 0>;
131 serial1: serial@54006900 {
132 compatible = "socionext,uniphier-uart";
134 reg = <0x54006900 0x40>;
135 interrupts = <0 35 4>;
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_uart1>;
138 clocks = <&peri_clk 1>;
139 clock-frequency = <58820000>;
140 resets = <&peri_rst 1>;
143 serial2: serial@54006a00 {
144 compatible = "socionext,uniphier-uart";
146 reg = <0x54006a00 0x40>;
147 interrupts = <0 37 4>;
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_uart2>;
150 clocks = <&peri_clk 2>;
151 clock-frequency = <58820000>;
152 resets = <&peri_rst 2>;
155 serial3: serial@54006b00 {
156 compatible = "socionext,uniphier-uart";
158 reg = <0x54006b00 0x40>;
159 interrupts = <0 177 4>;
160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_uart3>;
162 clocks = <&peri_clk 3>;
163 clock-frequency = <58820000>;
164 resets = <&peri_rst 3>;
167 gpio: gpio@55000000 {
168 compatible = "socionext,uniphier-gpio";
169 reg = <0x55000000 0x200>;
170 interrupt-parent = <&aidet>;
171 interrupt-controller;
172 #interrupt-cells = <2>;
175 gpio-ranges = <&pinctrl 0 0 0>,
181 gpio-ranges-group-names = "gpio_range0",
188 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
193 compatible = "socionext,uniphier-ld11-aio";
194 reg = <0x56000000 0x80000>;
195 interrupts = <0 144 4>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_aout1>,
200 clocks = <&sys_clk 40>;
202 resets = <&sys_rst 40>;
203 #sound-dai-cells = <1>;
204 socionext,syscon = <&soc_glue>;
212 i2s_pcmin2: endpoint {
219 remote-endpoint = <&evea_line>;
224 i2s_hpcmout1: endpoint {
231 remote-endpoint = <&evea_hp>;
235 spdif_port0: port@5 {
236 spdif_hiecout1: endpoint {
241 i2s_epcmout2: endpoint {
246 i2s_epcmout3: endpoint {
250 comp_spdif_port0: port@8 {
251 comp_spdif_hiecout1: endpoint {
257 compatible = "socionext,uniphier-evea";
258 reg = <0x57900000 0x1000>;
259 clock-names = "evea", "exiv";
260 clocks = <&sys_clk 41>, <&sys_clk 42>;
261 reset-names = "evea", "exiv", "adamv";
262 resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
263 #sound-dai-cells = <1>;
266 evea_line: endpoint {
267 remote-endpoint = <&i2s_line>;
273 remote-endpoint = <&i2s_hp>;
279 compatible = "socionext,uniphier-ld11-adamv",
280 "simple-mfd", "syscon";
281 reg = <0x57920000 0x1000>;
284 compatible = "socionext,uniphier-ld11-adamv-reset";
290 compatible = "socionext,uniphier-fi2c";
292 reg = <0x58780000 0x80>;
293 #address-cells = <1>;
295 interrupts = <0 41 4>;
296 pinctrl-names = "default";
297 pinctrl-0 = <&pinctrl_i2c0>;
298 clocks = <&peri_clk 4>;
299 resets = <&peri_rst 4>;
300 clock-frequency = <100000>;
304 compatible = "socionext,uniphier-fi2c";
306 reg = <0x58781000 0x80>;
307 #address-cells = <1>;
309 interrupts = <0 42 4>;
310 pinctrl-names = "default";
311 pinctrl-0 = <&pinctrl_i2c1>;
312 clocks = <&peri_clk 5>;
313 resets = <&peri_rst 5>;
314 clock-frequency = <100000>;
318 compatible = "socionext,uniphier-fi2c";
319 reg = <0x58782000 0x80>;
320 #address-cells = <1>;
322 interrupts = <0 43 4>;
323 clocks = <&peri_clk 6>;
324 resets = <&peri_rst 6>;
325 clock-frequency = <400000>;
329 compatible = "socionext,uniphier-fi2c";
331 reg = <0x58783000 0x80>;
332 #address-cells = <1>;
334 interrupts = <0 44 4>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&pinctrl_i2c3>;
337 clocks = <&peri_clk 7>;
338 resets = <&peri_rst 7>;
339 clock-frequency = <100000>;
343 compatible = "socionext,uniphier-fi2c";
345 reg = <0x58784000 0x80>;
346 #address-cells = <1>;
348 interrupts = <0 45 4>;
349 pinctrl-names = "default";
350 pinctrl-0 = <&pinctrl_i2c4>;
351 clocks = <&peri_clk 8>;
352 resets = <&peri_rst 8>;
353 clock-frequency = <100000>;
357 compatible = "socionext,uniphier-fi2c";
358 reg = <0x58785000 0x80>;
359 #address-cells = <1>;
361 interrupts = <0 25 4>;
362 clocks = <&peri_clk 9>;
363 resets = <&peri_rst 9>;
364 clock-frequency = <400000>;
367 system_bus: system-bus@58c00000 {
368 compatible = "socionext,uniphier-system-bus";
370 reg = <0x58c00000 0x400>;
371 #address-cells = <2>;
373 pinctrl-names = "default";
374 pinctrl-0 = <&pinctrl_system_bus>;
378 compatible = "socionext,uniphier-smpctrl";
379 reg = <0x59801000 0x400>;
383 compatible = "socionext,uniphier-ld11-sdctrl",
384 "simple-mfd", "syscon";
385 reg = <0x59810000 0x400>;
388 compatible = "socionext,uniphier-ld11-sd-reset";
394 compatible = "socionext,uniphier-ld11-perictrl",
395 "simple-mfd", "syscon";
396 reg = <0x59820000 0x200>;
399 compatible = "socionext,uniphier-ld11-peri-clock";
404 compatible = "socionext,uniphier-ld11-peri-reset";
409 emmc: sdhc@5a000000 {
410 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
411 reg = <0x5a000000 0x400>;
412 interrupts = <0 78 4>;
413 pinctrl-names = "default";
414 pinctrl-0 = <&pinctrl_emmc_1v8>;
415 clocks = <&sys_clk 4>;
416 resets = <&sys_rst 4>;
420 mmc-pwrseq = <&emmc_pwrseq>;
421 cdns,phy-input-delay-legacy = <4>;
422 cdns,phy-input-delay-mmc-highspeed = <2>;
423 cdns,phy-input-delay-mmc-ddr = <3>;
424 cdns,phy-dll-delay-sdclk = <21>;
425 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
429 compatible = "socionext,uniphier-ehci", "generic-ehci";
431 reg = <0x5a800100 0x100>;
432 interrupts = <0 243 4>;
433 pinctrl-names = "default";
434 pinctrl-0 = <&pinctrl_usb0>;
435 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
437 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
439 has-transaction-translator;
443 compatible = "socionext,uniphier-ehci", "generic-ehci";
445 reg = <0x5a810100 0x100>;
446 interrupts = <0 244 4>;
447 pinctrl-names = "default";
448 pinctrl-0 = <&pinctrl_usb1>;
449 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
451 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
453 has-transaction-translator;
457 compatible = "socionext,uniphier-ehci", "generic-ehci";
459 reg = <0x5a820100 0x100>;
460 interrupts = <0 245 4>;
461 pinctrl-names = "default";
462 pinctrl-0 = <&pinctrl_usb2>;
463 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
465 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
467 has-transaction-translator;
471 compatible = "socionext,uniphier-ld11-mioctrl",
472 "simple-mfd", "syscon";
473 reg = <0x5b3e0000 0x800>;
476 compatible = "socionext,uniphier-ld11-mio-clock";
481 compatible = "socionext,uniphier-ld11-mio-reset";
483 resets = <&sys_rst 7>;
487 soc_glue: soc-glue@5f800000 {
488 compatible = "socionext,uniphier-ld11-soc-glue",
489 "simple-mfd", "syscon";
490 reg = <0x5f800000 0x2000>;
493 compatible = "socionext,uniphier-ld11-pinctrl";
498 compatible = "socionext,uniphier-ld11-soc-glue-debug",
500 #address-cells = <1>;
502 ranges = <0 0x5f900000 0x2000>;
505 compatible = "socionext,uniphier-efuse";
510 compatible = "socionext,uniphier-efuse";
515 aidet: aidet@5fc20000 {
516 compatible = "socionext,uniphier-ld11-aidet";
517 reg = <0x5fc20000 0x200>;
518 interrupt-controller;
519 #interrupt-cells = <2>;
522 gic: interrupt-controller@5fe00000 {
523 compatible = "arm,gic-v3";
524 reg = <0x5fe00000 0x10000>, /* GICD */
525 <0x5fe40000 0x80000>; /* GICR */
526 interrupt-controller;
527 #interrupt-cells = <3>;
528 interrupts = <1 9 4>;
532 compatible = "socionext,uniphier-ld11-sysctrl",
533 "simple-mfd", "syscon";
534 reg = <0x61840000 0x10000>;
537 compatible = "socionext,uniphier-ld11-clock";
542 compatible = "socionext,uniphier-ld11-reset";
547 compatible = "socionext,uniphier-wdt";
551 eth: ethernet@65000000 {
552 compatible = "socionext,uniphier-ld11-ave4";
554 reg = <0x65000000 0x8500>;
555 interrupts = <0 66 4>;
556 clock-names = "ether";
557 clocks = <&sys_clk 6>;
558 reset-names = "ether";
559 resets = <&sys_rst 6>;
561 local-mac-address = [00 00 00 00 00 00];
562 socionext,syscon-phy-mode = <&soc_glue 0>;
565 #address-cells = <1>;
570 nand: nand@68000000 {
571 compatible = "socionext,uniphier-denali-nand-v5b";
573 reg-names = "nand_data", "denali_reg";
574 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
575 interrupts = <0 65 4>;
576 pinctrl-names = "default";
577 pinctrl-0 = <&pinctrl_nand>;
578 clocks = <&sys_clk 2>;
579 resets = <&sys_rst 2>;
584 #include "uniphier-pinctrl.dtsi"
587 drive-strength = <4>; /* default: 4mA */
591 drive-strength = <8>; /* 8mA */