2 * Device Tree Source for UniPhier LD11 SoC
4 * Copyright (C) 2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
46 /memreserve/ 0x80000000 0x00080000;
49 compatible = "socionext,uniphier-ld11";
52 interrupt-parent = <&gic>;
71 compatible = "arm,cortex-a53", "arm,armv8";
73 clocks = <&sys_clk 33>;
74 enable-method = "psci";
75 operating-points-v2 = <&cluster0_opp>;
80 compatible = "arm,cortex-a53", "arm,armv8";
82 clocks = <&sys_clk 33>;
83 enable-method = "psci";
84 operating-points-v2 = <&cluster0_opp>;
88 cluster0_opp: opp_table {
89 compatible = "operating-points-v2";
93 opp-hz = /bits/ 64 <245000000>;
94 clock-latency-ns = <300>;
97 opp-hz = /bits/ 64 <250000000>;
98 clock-latency-ns = <300>;
101 opp-hz = /bits/ 64 <490000000>;
102 clock-latency-ns = <300>;
105 opp-hz = /bits/ 64 <500000000>;
106 clock-latency-ns = <300>;
109 opp-hz = /bits/ 64 <653334000>;
110 clock-latency-ns = <300>;
113 opp-hz = /bits/ 64 <666667000>;
114 clock-latency-ns = <300>;
117 opp-hz = /bits/ 64 <980000000>;
118 clock-latency-ns = <300>;
123 compatible = "arm,psci-1.0";
129 compatible = "fixed-clock";
131 clock-frequency = <25000000>;
136 compatible = "arm,armv8-timer";
137 interrupts = <1 13 4>,
144 compatible = "simple-bus";
145 #address-cells = <1>;
147 ranges = <0 0 0 0xffffffff>;
150 serial0: serial@54006800 {
151 compatible = "socionext,uniphier-uart";
153 reg = <0x54006800 0x40>;
154 interrupts = <0 33 4>;
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_uart0>;
157 clocks = <&peri_clk 0>;
158 clock-frequency = <58820000>;
161 serial1: serial@54006900 {
162 compatible = "socionext,uniphier-uart";
164 reg = <0x54006900 0x40>;
165 interrupts = <0 35 4>;
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_uart1>;
168 clocks = <&peri_clk 1>;
169 clock-frequency = <58820000>;
172 serial2: serial@54006a00 {
173 compatible = "socionext,uniphier-uart";
175 reg = <0x54006a00 0x40>;
176 interrupts = <0 37 4>;
177 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_uart2>;
179 clocks = <&peri_clk 2>;
180 clock-frequency = <58820000>;
183 serial3: serial@54006b00 {
184 compatible = "socionext,uniphier-uart";
186 reg = <0x54006b00 0x40>;
187 interrupts = <0 177 4>;
188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_uart3>;
190 clocks = <&peri_clk 3>;
191 clock-frequency = <58820000>;
195 compatible = "socionext,uniphier-fi2c";
197 reg = <0x58780000 0x80>;
198 #address-cells = <1>;
200 interrupts = <0 41 4>;
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_i2c0>;
203 clocks = <&peri_clk 4>;
204 clock-frequency = <100000>;
208 compatible = "socionext,uniphier-fi2c";
210 reg = <0x58781000 0x80>;
211 #address-cells = <1>;
213 interrupts = <0 42 4>;
214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_i2c1>;
216 clocks = <&peri_clk 5>;
217 clock-frequency = <100000>;
221 compatible = "socionext,uniphier-fi2c";
222 reg = <0x58782000 0x80>;
223 #address-cells = <1>;
225 interrupts = <0 43 4>;
226 clocks = <&peri_clk 6>;
227 clock-frequency = <400000>;
231 compatible = "socionext,uniphier-fi2c";
233 reg = <0x58783000 0x80>;
234 #address-cells = <1>;
236 interrupts = <0 44 4>;
237 pinctrl-names = "default";
238 pinctrl-0 = <&pinctrl_i2c3>;
239 clocks = <&peri_clk 7>;
240 clock-frequency = <100000>;
244 compatible = "socionext,uniphier-fi2c";
246 reg = <0x58784000 0x80>;
247 #address-cells = <1>;
249 interrupts = <0 45 4>;
250 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_i2c4>;
252 clocks = <&peri_clk 8>;
253 clock-frequency = <100000>;
257 compatible = "socionext,uniphier-fi2c";
258 reg = <0x58785000 0x80>;
259 #address-cells = <1>;
261 interrupts = <0 25 4>;
262 clocks = <&peri_clk 9>;
263 clock-frequency = <400000>;
266 system_bus: system-bus@58c00000 {
267 compatible = "socionext,uniphier-system-bus";
269 reg = <0x58c00000 0x400>;
270 #address-cells = <2>;
272 pinctrl-names = "default";
273 pinctrl-0 = <&pinctrl_system_bus>;
277 compatible = "socionext,uniphier-smpctrl";
278 reg = <0x59801000 0x400>;
282 compatible = "socionext,uniphier-ld11-sdctrl",
283 "simple-mfd", "syscon";
284 reg = <0x59810000 0x400>;
287 compatible = "socionext,uniphier-ld11-sd-reset";
293 compatible = "socionext,uniphier-ld11-perictrl",
294 "simple-mfd", "syscon";
295 reg = <0x59820000 0x200>;
298 compatible = "socionext,uniphier-ld11-peri-clock";
303 compatible = "socionext,uniphier-ld11-peri-reset";
308 emmc: sdhc@5a000000 {
309 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
310 reg = <0x5a000000 0x400>;
311 interrupts = <0 78 4>;
312 pinctrl-names = "default";
313 pinctrl-0 = <&pinctrl_emmc_1v8>;
314 clocks = <&sys_clk 4>;
318 cdns,phy-input-delay-legacy = <4>;
319 cdns,phy-input-delay-mmc-highspeed = <2>;
320 cdns,phy-input-delay-mmc-ddr = <3>;
321 cdns,phy-dll-delay-sdclk = <21>;
322 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
326 compatible = "socionext,uniphier-ehci", "generic-ehci";
328 reg = <0x5a800100 0x100>;
329 interrupts = <0 243 4>;
330 pinctrl-names = "default";
331 pinctrl-0 = <&pinctrl_usb0>;
332 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
333 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
338 compatible = "socionext,uniphier-ehci", "generic-ehci";
340 reg = <0x5a810100 0x100>;
341 interrupts = <0 244 4>;
342 pinctrl-names = "default";
343 pinctrl-0 = <&pinctrl_usb1>;
344 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
345 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
350 compatible = "socionext,uniphier-ehci", "generic-ehci";
352 reg = <0x5a820100 0x100>;
353 interrupts = <0 245 4>;
354 pinctrl-names = "default";
355 pinctrl-0 = <&pinctrl_usb2>;
356 clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
357 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
362 compatible = "socionext,uniphier-ld11-mioctrl",
363 "simple-mfd", "syscon";
364 reg = <0x5b3e0000 0x800>;
367 compatible = "socionext,uniphier-ld11-mio-clock";
372 compatible = "socionext,uniphier-ld11-mio-reset";
374 resets = <&sys_rst 7>;
379 compatible = "socionext,uniphier-ld11-soc-glue",
380 "simple-mfd", "syscon";
381 reg = <0x5f800000 0x2000>;
385 compatible = "socionext,uniphier-ld11-pinctrl";
391 compatible = "simple-mfd", "syscon";
392 reg = <0x5fc20000 0x200>;
395 gic: interrupt-controller@5fe00000 {
396 compatible = "arm,gic-v3";
397 reg = <0x5fe00000 0x10000>, /* GICD */
398 <0x5fe40000 0x80000>; /* GICR */
399 interrupt-controller;
400 #interrupt-cells = <3>;
401 interrupts = <1 9 4>;
405 compatible = "socionext,uniphier-ld11-sysctrl",
406 "simple-mfd", "syscon";
407 reg = <0x61840000 0x10000>;
410 compatible = "socionext,uniphier-ld11-clock";
415 compatible = "socionext,uniphier-ld11-reset";
420 nand: nand@68000000 {
421 compatible = "socionext,uniphier-denali-nand-v5b";
423 reg-names = "nand_data", "denali_reg";
424 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
425 interrupts = <0 65 4>;
426 pinctrl-names = "default";
427 pinctrl-0 = <&pinctrl_nand>;
428 clocks = <&sys_clk 2>;
429 nand-ecc-strength = <8>;
434 /include/ "uniphier-pinctrl.dtsi"