2 * Device Tree Source for UniPhier LD11 SoC
4 * Copyright (C) 2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/gpio/uniphier-gpio.h>
13 /memreserve/ 0x80000000 0x02000000;
16 compatible = "socionext,uniphier-ld11";
19 interrupt-parent = <&gic>;
38 compatible = "arm,cortex-a53", "arm,armv8";
40 clocks = <&sys_clk 33>;
41 enable-method = "psci";
42 operating-points-v2 = <&cluster0_opp>;
47 compatible = "arm,cortex-a53", "arm,armv8";
49 clocks = <&sys_clk 33>;
50 enable-method = "psci";
51 operating-points-v2 = <&cluster0_opp>;
55 cluster0_opp: opp-table {
56 compatible = "operating-points-v2";
60 opp-hz = /bits/ 64 <245000000>;
61 clock-latency-ns = <300>;
64 opp-hz = /bits/ 64 <250000000>;
65 clock-latency-ns = <300>;
68 opp-hz = /bits/ 64 <490000000>;
69 clock-latency-ns = <300>;
72 opp-hz = /bits/ 64 <500000000>;
73 clock-latency-ns = <300>;
76 opp-hz = /bits/ 64 <653334000>;
77 clock-latency-ns = <300>;
80 opp-hz = /bits/ 64 <666667000>;
81 clock-latency-ns = <300>;
84 opp-hz = /bits/ 64 <980000000>;
85 clock-latency-ns = <300>;
90 compatible = "arm,psci-1.0";
96 compatible = "fixed-clock";
98 clock-frequency = <25000000>;
102 emmc_pwrseq: emmc-pwrseq {
103 compatible = "mmc-pwrseq-emmc";
104 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
108 compatible = "arm,armv8-timer";
109 interrupts = <1 13 4>,
116 compatible = "simple-bus";
117 #address-cells = <1>;
119 ranges = <0 0 0 0xffffffff>;
121 serial0: serial@54006800 {
122 compatible = "socionext,uniphier-uart";
124 reg = <0x54006800 0x40>;
125 interrupts = <0 33 4>;
126 pinctrl-names = "default";
127 pinctrl-0 = <&pinctrl_uart0>;
128 clocks = <&peri_clk 0>;
129 clock-frequency = <58820000>;
130 resets = <&peri_rst 0>;
133 serial1: serial@54006900 {
134 compatible = "socionext,uniphier-uart";
136 reg = <0x54006900 0x40>;
137 interrupts = <0 35 4>;
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_uart1>;
140 clocks = <&peri_clk 1>;
141 clock-frequency = <58820000>;
142 resets = <&peri_rst 1>;
145 serial2: serial@54006a00 {
146 compatible = "socionext,uniphier-uart";
148 reg = <0x54006a00 0x40>;
149 interrupts = <0 37 4>;
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_uart2>;
152 clocks = <&peri_clk 2>;
153 clock-frequency = <58820000>;
154 resets = <&peri_rst 2>;
157 serial3: serial@54006b00 {
158 compatible = "socionext,uniphier-uart";
160 reg = <0x54006b00 0x40>;
161 interrupts = <0 177 4>;
162 pinctrl-names = "default";
163 pinctrl-0 = <&pinctrl_uart3>;
164 clocks = <&peri_clk 3>;
165 clock-frequency = <58820000>;
166 resets = <&peri_rst 3>;
169 gpio: gpio@55000000 {
170 compatible = "socionext,uniphier-gpio";
171 reg = <0x55000000 0x200>;
172 interrupt-parent = <&aidet>;
173 interrupt-controller;
174 #interrupt-cells = <2>;
177 gpio-ranges = <&pinctrl 0 0 0>,
183 gpio-ranges-group-names = "gpio_range0",
190 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
195 compatible = "socionext,uniphier-ld11-adamv",
196 "simple-mfd", "syscon";
197 reg = <0x57920000 0x1000>;
200 compatible = "socionext,uniphier-ld11-adamv-reset";
206 compatible = "socionext,uniphier-fi2c";
208 reg = <0x58780000 0x80>;
209 #address-cells = <1>;
211 interrupts = <0 41 4>;
212 pinctrl-names = "default";
213 pinctrl-0 = <&pinctrl_i2c0>;
214 clocks = <&peri_clk 4>;
215 resets = <&peri_rst 4>;
216 clock-frequency = <100000>;
220 compatible = "socionext,uniphier-fi2c";
222 reg = <0x58781000 0x80>;
223 #address-cells = <1>;
225 interrupts = <0 42 4>;
226 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_i2c1>;
228 clocks = <&peri_clk 5>;
229 resets = <&peri_rst 5>;
230 clock-frequency = <100000>;
234 compatible = "socionext,uniphier-fi2c";
235 reg = <0x58782000 0x80>;
236 #address-cells = <1>;
238 interrupts = <0 43 4>;
239 clocks = <&peri_clk 6>;
240 resets = <&peri_rst 6>;
241 clock-frequency = <400000>;
245 compatible = "socionext,uniphier-fi2c";
247 reg = <0x58783000 0x80>;
248 #address-cells = <1>;
250 interrupts = <0 44 4>;
251 pinctrl-names = "default";
252 pinctrl-0 = <&pinctrl_i2c3>;
253 clocks = <&peri_clk 7>;
254 resets = <&peri_rst 7>;
255 clock-frequency = <100000>;
259 compatible = "socionext,uniphier-fi2c";
261 reg = <0x58784000 0x80>;
262 #address-cells = <1>;
264 interrupts = <0 45 4>;
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_i2c4>;
267 clocks = <&peri_clk 8>;
268 resets = <&peri_rst 8>;
269 clock-frequency = <100000>;
273 compatible = "socionext,uniphier-fi2c";
274 reg = <0x58785000 0x80>;
275 #address-cells = <1>;
277 interrupts = <0 25 4>;
278 clocks = <&peri_clk 9>;
279 resets = <&peri_rst 9>;
280 clock-frequency = <400000>;
283 system_bus: system-bus@58c00000 {
284 compatible = "socionext,uniphier-system-bus";
286 reg = <0x58c00000 0x400>;
287 #address-cells = <2>;
289 pinctrl-names = "default";
290 pinctrl-0 = <&pinctrl_system_bus>;
294 compatible = "socionext,uniphier-smpctrl";
295 reg = <0x59801000 0x400>;
299 compatible = "socionext,uniphier-ld11-sdctrl",
300 "simple-mfd", "syscon";
301 reg = <0x59810000 0x400>;
304 compatible = "socionext,uniphier-ld11-sd-reset";
310 compatible = "socionext,uniphier-ld11-perictrl",
311 "simple-mfd", "syscon";
312 reg = <0x59820000 0x200>;
315 compatible = "socionext,uniphier-ld11-peri-clock";
320 compatible = "socionext,uniphier-ld11-peri-reset";
325 emmc: sdhc@5a000000 {
326 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
327 reg = <0x5a000000 0x400>;
328 interrupts = <0 78 4>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_emmc_1v8>;
331 clocks = <&sys_clk 4>;
332 resets = <&sys_rst 4>;
336 mmc-pwrseq = <&emmc_pwrseq>;
337 cdns,phy-input-delay-legacy = <4>;
338 cdns,phy-input-delay-mmc-highspeed = <2>;
339 cdns,phy-input-delay-mmc-ddr = <3>;
340 cdns,phy-dll-delay-sdclk = <21>;
341 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
345 compatible = "socionext,uniphier-ehci", "generic-ehci";
347 reg = <0x5a800100 0x100>;
348 interrupts = <0 243 4>;
349 pinctrl-names = "default";
350 pinctrl-0 = <&pinctrl_usb0>;
351 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
353 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
358 compatible = "socionext,uniphier-ehci", "generic-ehci";
360 reg = <0x5a810100 0x100>;
361 interrupts = <0 244 4>;
362 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_usb1>;
364 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
366 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
371 compatible = "socionext,uniphier-ehci", "generic-ehci";
373 reg = <0x5a820100 0x100>;
374 interrupts = <0 245 4>;
375 pinctrl-names = "default";
376 pinctrl-0 = <&pinctrl_usb2>;
377 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
379 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
384 compatible = "socionext,uniphier-ld11-mioctrl",
385 "simple-mfd", "syscon";
386 reg = <0x5b3e0000 0x800>;
389 compatible = "socionext,uniphier-ld11-mio-clock";
394 compatible = "socionext,uniphier-ld11-mio-reset";
396 resets = <&sys_rst 7>;
401 compatible = "socionext,uniphier-ld11-soc-glue",
402 "simple-mfd", "syscon";
403 reg = <0x5f800000 0x2000>;
406 compatible = "socionext,uniphier-ld11-pinctrl";
411 compatible = "socionext,uniphier-ld11-soc-glue-debug",
413 #address-cells = <1>;
415 ranges = <0 0x5f900000 0x2000>;
418 compatible = "socionext,uniphier-efuse";
423 compatible = "socionext,uniphier-efuse";
428 aidet: aidet@5fc20000 {
429 compatible = "socionext,uniphier-ld11-aidet";
430 reg = <0x5fc20000 0x200>;
431 interrupt-controller;
432 #interrupt-cells = <2>;
435 gic: interrupt-controller@5fe00000 {
436 compatible = "arm,gic-v3";
437 reg = <0x5fe00000 0x10000>, /* GICD */
438 <0x5fe40000 0x80000>; /* GICR */
439 interrupt-controller;
440 #interrupt-cells = <3>;
441 interrupts = <1 9 4>;
445 compatible = "socionext,uniphier-ld11-sysctrl",
446 "simple-mfd", "syscon";
447 reg = <0x61840000 0x10000>;
450 compatible = "socionext,uniphier-ld11-clock";
455 compatible = "socionext,uniphier-ld11-reset";
460 compatible = "socionext,uniphier-wdt";
464 nand: nand@68000000 {
465 compatible = "socionext,uniphier-denali-nand-v5b";
467 reg-names = "nand_data", "denali_reg";
468 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
469 interrupts = <0 65 4>;
470 pinctrl-names = "default";
471 pinctrl-0 = <&pinctrl_nand>;
472 clocks = <&sys_clk 2>;
473 resets = <&sys_rst 2>;
478 #include "uniphier-pinctrl.dtsi"