2 * Device Tree Source for UniPhier LD11 SoC
4 * Copyright (C) 2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 /memreserve/ 0x80000000 0x02000000;
13 compatible = "socionext,uniphier-ld11";
16 interrupt-parent = <&gic>;
35 compatible = "arm,cortex-a53", "arm,armv8";
37 clocks = <&sys_clk 33>;
38 enable-method = "psci";
39 operating-points-v2 = <&cluster0_opp>;
44 compatible = "arm,cortex-a53", "arm,armv8";
46 clocks = <&sys_clk 33>;
47 enable-method = "psci";
48 operating-points-v2 = <&cluster0_opp>;
52 cluster0_opp: opp_table {
53 compatible = "operating-points-v2";
57 opp-hz = /bits/ 64 <245000000>;
58 clock-latency-ns = <300>;
61 opp-hz = /bits/ 64 <250000000>;
62 clock-latency-ns = <300>;
65 opp-hz = /bits/ 64 <490000000>;
66 clock-latency-ns = <300>;
69 opp-hz = /bits/ 64 <500000000>;
70 clock-latency-ns = <300>;
73 opp-hz = /bits/ 64 <653334000>;
74 clock-latency-ns = <300>;
77 opp-hz = /bits/ 64 <666667000>;
78 clock-latency-ns = <300>;
81 opp-hz = /bits/ 64 <980000000>;
82 clock-latency-ns = <300>;
87 compatible = "arm,psci-1.0";
93 compatible = "fixed-clock";
95 clock-frequency = <25000000>;
100 compatible = "arm,armv8-timer";
101 interrupts = <1 13 4>,
108 compatible = "simple-bus";
109 #address-cells = <1>;
111 ranges = <0 0 0 0xffffffff>;
113 serial0: serial@54006800 {
114 compatible = "socionext,uniphier-uart";
116 reg = <0x54006800 0x40>;
117 interrupts = <0 33 4>;
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_uart0>;
120 clocks = <&peri_clk 0>;
121 clock-frequency = <58820000>;
124 serial1: serial@54006900 {
125 compatible = "socionext,uniphier-uart";
127 reg = <0x54006900 0x40>;
128 interrupts = <0 35 4>;
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_uart1>;
131 clocks = <&peri_clk 1>;
132 clock-frequency = <58820000>;
135 serial2: serial@54006a00 {
136 compatible = "socionext,uniphier-uart";
138 reg = <0x54006a00 0x40>;
139 interrupts = <0 37 4>;
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_uart2>;
142 clocks = <&peri_clk 2>;
143 clock-frequency = <58820000>;
146 serial3: serial@54006b00 {
147 compatible = "socionext,uniphier-uart";
149 reg = <0x54006b00 0x40>;
150 interrupts = <0 177 4>;
151 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_uart3>;
153 clocks = <&peri_clk 3>;
154 clock-frequency = <58820000>;
157 gpio: gpio@55000000 {
158 compatible = "socionext,uniphier-gpio";
159 reg = <0x55000000 0x200>;
160 interrupt-parent = <&aidet>;
161 interrupt-controller;
162 #interrupt-cells = <2>;
165 gpio-ranges = <&pinctrl 0 0 0>,
171 gpio-ranges-group-names = "gpio_range0",
181 compatible = "socionext,uniphier-fi2c";
183 reg = <0x58780000 0x80>;
184 #address-cells = <1>;
186 interrupts = <0 41 4>;
187 pinctrl-names = "default";
188 pinctrl-0 = <&pinctrl_i2c0>;
189 clocks = <&peri_clk 4>;
190 clock-frequency = <100000>;
194 compatible = "socionext,uniphier-fi2c";
196 reg = <0x58781000 0x80>;
197 #address-cells = <1>;
199 interrupts = <0 42 4>;
200 pinctrl-names = "default";
201 pinctrl-0 = <&pinctrl_i2c1>;
202 clocks = <&peri_clk 5>;
203 clock-frequency = <100000>;
207 compatible = "socionext,uniphier-fi2c";
208 reg = <0x58782000 0x80>;
209 #address-cells = <1>;
211 interrupts = <0 43 4>;
212 clocks = <&peri_clk 6>;
213 clock-frequency = <400000>;
217 compatible = "socionext,uniphier-fi2c";
219 reg = <0x58783000 0x80>;
220 #address-cells = <1>;
222 interrupts = <0 44 4>;
223 pinctrl-names = "default";
224 pinctrl-0 = <&pinctrl_i2c3>;
225 clocks = <&peri_clk 7>;
226 clock-frequency = <100000>;
230 compatible = "socionext,uniphier-fi2c";
232 reg = <0x58784000 0x80>;
233 #address-cells = <1>;
235 interrupts = <0 45 4>;
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_i2c4>;
238 clocks = <&peri_clk 8>;
239 clock-frequency = <100000>;
243 compatible = "socionext,uniphier-fi2c";
244 reg = <0x58785000 0x80>;
245 #address-cells = <1>;
247 interrupts = <0 25 4>;
248 clocks = <&peri_clk 9>;
249 clock-frequency = <400000>;
252 system_bus: system-bus@58c00000 {
253 compatible = "socionext,uniphier-system-bus";
255 reg = <0x58c00000 0x400>;
256 #address-cells = <2>;
258 pinctrl-names = "default";
259 pinctrl-0 = <&pinctrl_system_bus>;
263 compatible = "socionext,uniphier-smpctrl";
264 reg = <0x59801000 0x400>;
268 compatible = "socionext,uniphier-ld11-sdctrl",
269 "simple-mfd", "syscon";
270 reg = <0x59810000 0x400>;
273 compatible = "socionext,uniphier-ld11-sd-reset";
279 compatible = "socionext,uniphier-ld11-perictrl",
280 "simple-mfd", "syscon";
281 reg = <0x59820000 0x200>;
284 compatible = "socionext,uniphier-ld11-peri-clock";
289 compatible = "socionext,uniphier-ld11-peri-reset";
294 emmc: sdhc@5a000000 {
295 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
296 reg = <0x5a000000 0x400>;
297 interrupts = <0 78 4>;
298 pinctrl-names = "default";
299 pinctrl-0 = <&pinctrl_emmc_1v8>;
300 clocks = <&sys_clk 4>;
304 cdns,phy-input-delay-legacy = <4>;
305 cdns,phy-input-delay-mmc-highspeed = <2>;
306 cdns,phy-input-delay-mmc-ddr = <3>;
307 cdns,phy-dll-delay-sdclk = <21>;
308 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
312 compatible = "socionext,uniphier-ehci", "generic-ehci";
314 reg = <0x5a800100 0x100>;
315 interrupts = <0 243 4>;
316 pinctrl-names = "default";
317 pinctrl-0 = <&pinctrl_usb0>;
318 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
319 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
324 compatible = "socionext,uniphier-ehci", "generic-ehci";
326 reg = <0x5a810100 0x100>;
327 interrupts = <0 244 4>;
328 pinctrl-names = "default";
329 pinctrl-0 = <&pinctrl_usb1>;
330 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
331 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
336 compatible = "socionext,uniphier-ehci", "generic-ehci";
338 reg = <0x5a820100 0x100>;
339 interrupts = <0 245 4>;
340 pinctrl-names = "default";
341 pinctrl-0 = <&pinctrl_usb2>;
342 clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
343 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
348 compatible = "socionext,uniphier-ld11-mioctrl",
349 "simple-mfd", "syscon";
350 reg = <0x5b3e0000 0x800>;
353 compatible = "socionext,uniphier-ld11-mio-clock";
358 compatible = "socionext,uniphier-ld11-mio-reset";
360 resets = <&sys_rst 7>;
365 compatible = "socionext,uniphier-ld11-soc-glue",
366 "simple-mfd", "syscon";
367 reg = <0x5f800000 0x2000>;
370 compatible = "socionext,uniphier-ld11-pinctrl";
374 aidet: aidet@5fc20000 {
375 compatible = "socionext,uniphier-ld11-aidet";
376 reg = <0x5fc20000 0x200>;
377 interrupt-controller;
378 #interrupt-cells = <2>;
381 gic: interrupt-controller@5fe00000 {
382 compatible = "arm,gic-v3";
383 reg = <0x5fe00000 0x10000>, /* GICD */
384 <0x5fe40000 0x80000>; /* GICR */
385 interrupt-controller;
386 #interrupt-cells = <3>;
387 interrupts = <1 9 4>;
391 compatible = "socionext,uniphier-ld11-sysctrl",
392 "simple-mfd", "syscon";
393 reg = <0x61840000 0x10000>;
396 compatible = "socionext,uniphier-ld11-clock";
401 compatible = "socionext,uniphier-ld11-reset";
406 compatible = "socionext,uniphier-wdt";
410 nand: nand@68000000 {
411 compatible = "socionext,uniphier-denali-nand-v5b";
413 reg-names = "nand_data", "denali_reg";
414 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
415 interrupts = <0 65 4>;
416 pinctrl-names = "default";
417 pinctrl-0 = <&pinctrl_nand>;
418 clocks = <&sys_clk 2>;
423 #include "uniphier-pinctrl.dtsi"