2 * Device Tree Source commonly used by UniPhier ARM SoCs
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: GPL-2.0+ X11
10 /include/ "skeleton.dtsi"
14 compatible = "arm,psci-0.2";
21 compatible = "fixed-clock";
26 compatible = "simple-bus";
30 interrupt-parent = <&intc>;
33 serial0: serial@54006800 {
34 compatible = "socionext,uniphier-uart";
36 reg = <0x54006800 0x40>;
37 interrupts = <0 33 4>;
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_uart0>;
40 clocks = <&peri_clk 0>;
43 serial1: serial@54006900 {
44 compatible = "socionext,uniphier-uart";
46 reg = <0x54006900 0x40>;
47 interrupts = <0 35 4>;
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_uart1>;
50 clocks = <&peri_clk 1>;
53 serial2: serial@54006a00 {
54 compatible = "socionext,uniphier-uart";
56 reg = <0x54006a00 0x40>;
57 interrupts = <0 37 4>;
58 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_uart2>;
60 clocks = <&peri_clk 2>;
63 serial3: serial@54006b00 {
64 compatible = "socionext,uniphier-uart";
66 reg = <0x54006b00 0x40>;
67 interrupts = <0 177 4>;
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_uart3>;
70 clocks = <&peri_clk 3>;
73 system_bus: system-bus@58c00000 {
74 compatible = "socionext,uniphier-system-bus";
76 reg = <0x58c00000 0x400>;
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_system_bus>;
84 compatible = "socionext,uniphier-smpctrl";
85 reg = <0x59801000 0x400>;
89 compatible = "socionext,uniphier-mioctrl",
90 "simple-mfd", "syscon";
91 reg = <0x59810000 0x800>;
104 compatible = "socionext,uniphier-perictrl",
105 "simple-mfd", "syscon";
106 reg = <0x59820000 0x200>;
118 compatible = "arm,cortex-a9-global-timer";
119 reg = <0x60000200 0x20>;
120 interrupts = <1 11 0x104>;
121 clocks = <&arm_timer_clk>;
125 compatible = "arm,cortex-a9-twd-timer";
126 reg = <0x60000600 0x20>;
127 interrupts = <1 13 0x104>;
128 clocks = <&arm_timer_clk>;
131 intc: interrupt-controller@60001000 {
132 compatible = "arm,cortex-a9-gic";
133 reg = <0x60001000 0x1000>,
135 #interrupt-cells = <3>;
136 interrupt-controller;
140 compatible = "socionext,uniphier-soc-glue",
141 "simple-mfd", "syscon";
142 reg = <0x5f800000 0x2000>;
146 /* specify compatible in each SoC DTSI */
152 compatible = "socionext,uniphier-sysctrl",
153 "simple-mfd", "syscon";
154 reg = <0x61840000 0x4000>;
165 nand: nand@68000000 {
166 compatible = "denali,denali-nand-dt";
168 reg-names = "nand_data", "denali_reg";
169 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
170 interrupts = <0 65 4>;
171 pinctrl-names = "default";
172 pinctrl-0 = <&pinctrl_nand>;
177 /include/ "uniphier-pinctrl.dtsi"