arm64: zynqmp: Use only earlycon bootargs instead of full one
[oweals/u-boot.git] / arch / arm / dts / tegra20-paz00.dts
1 /dts-v1/;
2
3 #include <dt-bindings/input/input.h>
4 #include "tegra20.dtsi"
5
6 / {
7         model = "Toshiba AC100 / Dynabook AZ";
8         compatible = "compal,paz00", "nvidia,tegra20";
9
10         chosen {
11                 stdout-path = &uarta;
12         };
13
14         aliases {
15                 rtc0 = "/i2c@7000d000/tps6586x@34";
16                 rtc1 = "/rtc@7000e000";
17                 serial0 = &uarta;
18                 serial1 = &uartc;
19                 usb0 = "/usb@c5000000";
20                 usb1 = "/usb@c5004000";
21                 usb2 = "/usb@c5008000";
22                 mmc0 = "/sdhci@c8000600";
23                 mmc1 = "/sdhci@c8000000";
24         };
25
26         memory {
27                 reg = <0x00000000 0x20000000>;
28         };
29
30         host1x@50000000 {
31                 status = "okay";
32                 dc@54200000 {
33                         status = "okay";
34                         rgb {
35                                 status = "okay";
36
37                                 nvidia,panel = <&panel>;
38
39                                 display-timings {
40                                         timing@0 {
41                                                 /* PAZ00 has 1024x600 */
42                                                 clock-frequency = <54030000>;
43                                                 hactive = <1024>;
44                                                 vactive = <600>;
45                                                 hback-porch = <160>;
46                                                 hfront-porch = <24>;
47                                                 hsync-len = <136>;
48                                                 vback-porch = <3>;
49                                                 vfront-porch = <61>;
50                                                 vsync-len = <6>;
51                                                 hsync-active = <1>;
52                                         };
53                                 };
54                         };
55                 };
56
57                 hdmi@54280000 {
58                         status = "okay";
59
60                         vdd-supply = <&hdmi_vdd_reg>;
61                         pll-supply = <&hdmi_pll_reg>;
62
63                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
64                         nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
65                                 GPIO_ACTIVE_HIGH>;
66                 };
67         };
68
69         pinmux@70000014 {
70                 pinctrl-names = "default";
71                 pinctrl-0 = <&state_default>;
72
73                 state_default: pinmux {
74                         ata {
75                                 nvidia,pins = "ata", "atc", "atd", "ate",
76                                         "dap2", "gmb", "gmc", "gmd", "spia",
77                                         "spib", "spic", "spid", "spie";
78                                 nvidia,function = "gmi";
79                         };
80                         atb {
81                                 nvidia,pins = "atb", "gma", "gme";
82                                 nvidia,function = "sdio4";
83                         };
84                         cdev1 {
85                                 nvidia,pins = "cdev1";
86                                 nvidia,function = "plla_out";
87                         };
88                         cdev2 {
89                                 nvidia,pins = "cdev2";
90                                 nvidia,function = "pllp_out4";
91                         };
92                         crtp {
93                                 nvidia,pins = "crtp";
94                                 nvidia,function = "crt";
95                         };
96                         csus {
97                                 nvidia,pins = "csus";
98                                 nvidia,function = "pllc_out1";
99                         };
100                         dap1 {
101                                 nvidia,pins = "dap1";
102                                 nvidia,function = "dap1";
103                         };
104                         dap3 {
105                                 nvidia,pins = "dap3";
106                                 nvidia,function = "dap3";
107                         };
108                         dap4 {
109                                 nvidia,pins = "dap4";
110                                 nvidia,function = "dap4";
111                         };
112                         ddc {
113                                 nvidia,pins = "ddc";
114                                 nvidia,function = "i2c2";
115                         };
116                         dta {
117                                 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
118                                 nvidia,function = "rsvd1";
119                         };
120                         dtf {
121                                 nvidia,pins = "dtf";
122                                 nvidia,function = "i2c3";
123                         };
124                         gpu {
125                                 nvidia,pins = "gpu", "sdb", "sdd";
126                                 nvidia,function = "pwm";
127                         };
128                         gpu7 {
129                                 nvidia,pins = "gpu7";
130                                 nvidia,function = "rtck";
131                         };
132                         gpv {
133                                 nvidia,pins = "gpv", "slxa", "slxk";
134                                 nvidia,function = "pcie";
135                         };
136                         hdint {
137                                 nvidia,pins = "hdint", "pta";
138                                 nvidia,function = "hdmi";
139                         };
140                         i2cp {
141                                 nvidia,pins = "i2cp";
142                                 nvidia,function = "i2cp";
143                         };
144                         irrx {
145                                 nvidia,pins = "irrx", "irtx";
146                                 nvidia,function = "uarta";
147                         };
148                         kbca {
149                                 nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
150                                 nvidia,function = "kbc";
151                         };
152                         kbcb {
153                                 nvidia,pins = "kbcb", "kbcd";
154                                 nvidia,function = "sdio2";
155                         };
156                         lcsn {
157                                 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
158                                         "ld3", "ld4", "ld5", "ld6", "ld7",
159                                         "ld8", "ld9", "ld10", "ld11", "ld12",
160                                         "ld13", "ld14", "ld15", "ld16", "ld17",
161                                         "ldc", "ldi", "lhp0", "lhp1", "lhp2",
162                                         "lhs", "lm0", "lm1", "lpp", "lpw0",
163                                         "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
164                                         "lsda", "lsdi", "lspi", "lvp0", "lvp1",
165                                         "lvs";
166                                 nvidia,function = "displaya";
167                         };
168                         owc {
169                                 nvidia,pins = "owc";
170                                 nvidia,function = "owr";
171                         };
172                         pmc {
173                                 nvidia,pins = "pmc";
174                                 nvidia,function = "pwr_on";
175                         };
176                         rm {
177                                 nvidia,pins = "rm";
178                                 nvidia,function = "i2c1";
179                         };
180                         sdc {
181                                 nvidia,pins = "sdc";
182                                 nvidia,function = "twc";
183                         };
184                         sdio1 {
185                                 nvidia,pins = "sdio1";
186                                 nvidia,function = "sdio1";
187                         };
188                         slxc {
189                                 nvidia,pins = "slxc", "slxd";
190                                 nvidia,function = "spi4";
191                         };
192                         spdi {
193                                 nvidia,pins = "spdi", "spdo";
194                                 nvidia,function = "rsvd2";
195                         };
196                         spif {
197                                 nvidia,pins = "spif", "uac";
198                                 nvidia,function = "rsvd4";
199                         };
200                         spig {
201                                 nvidia,pins = "spig", "spih";
202                                 nvidia,function = "spi2_alt";
203                         };
204                         uaa {
205                                 nvidia,pins = "uaa", "uab", "uda";
206                                 nvidia,function = "ulpi";
207                         };
208                         uad {
209                                 nvidia,pins = "uad";
210                                 nvidia,function = "spdif";
211                         };
212                         uca {
213                                 nvidia,pins = "uca", "ucb";
214                                 nvidia,function = "uartc";
215                         };
216                         conf_ata {
217                                 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
218                                         "cdev1", "cdev2", "dap1", "dap2", "dtf",
219                                         "gma", "gmb", "gmc", "gmd", "gme",
220                                         "gpu", "gpu7", "gpv", "i2cp", "pta",
221                                         "rm", "sdio1", "slxk", "spdo", "uac",
222                                         "uda";
223                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
224                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
225                         };
226                         conf_ck32 {
227                                 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
228                                         "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
229                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
230                         };
231                         conf_crtp {
232                                 nvidia,pins = "crtp", "dap3", "dap4", "dtb",
233                                         "dtc", "dte", "slxa", "slxc", "slxd",
234                                         "spdi";
235                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
236                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
237                         };
238                         conf_csus {
239                                 nvidia,pins = "csus", "spia", "spib", "spid",
240                                         "spif";
241                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
242                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
243                         };
244                         conf_ddc {
245                                 nvidia,pins = "ddc", "irrx", "irtx", "kbca",
246                                         "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
247                                         "spic", "spig", "uaa", "uab";
248                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
249                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
250                         };
251                         conf_dta {
252                                 nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
253                                         "spie", "spih", "uad", "uca", "ucb";
254                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
255                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
256                         };
257                         conf_hdint {
258                                 nvidia,pins = "hdint", "ld0", "ld1", "ld2",
259                                         "ld3", "ld4", "ld5", "ld6", "ld7",
260                                         "ld8", "ld9", "ld10", "ld11", "ld12",
261                                         "ld13", "ld14", "ld15", "ld16", "ld17",
262                                         "ldc", "ldi", "lhs", "lsc0", "lspi",
263                                         "lvs", "pmc";
264                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
265                         };
266                         conf_lc {
267                                 nvidia,pins = "lc", "ls";
268                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
269                         };
270                         conf_lcsn {
271                                 nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
272                                         "lm0", "lm1", "lpp", "lpw0", "lpw1",
273                                         "lpw2", "lsc1", "lsck", "lsda", "lsdi",
274                                         "lvp0", "lvp1", "sdb";
275                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
276                         };
277                         conf_ld17_0 {
278                                 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
279                                         "ld23_22";
280                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
281                         };
282                 };
283         };
284
285         i2s@70002800 {
286                 status = "okay";
287         };
288
289         serial@70006000 {
290                 status = "okay";
291         };
292
293         serial@70006200 {
294                 status = "okay";
295         };
296
297         pwm: pwm@7000a000 {
298                 status = "okay";
299         };
300
301         lvds_ddc: i2c@7000c000 {
302                 status = "okay";
303                 clock-frequency = <400000>;
304
305                 alc5632: alc5632@1e {
306                         compatible = "realtek,alc5632";
307                         reg = <0x1e>;
308                         gpio-controller;
309                         #gpio-cells = <2>;
310                 };
311         };
312
313         hdmi_ddc: i2c@7000c400 {
314                 status = "okay";
315                 clock-frequency = <100000>;
316         };
317
318         nvec@7000c500 {
319                 compatible = "nvidia,nvec";
320                 reg = <0x7000c500 0x100>;
321                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
322                 #address-cells = <1>;
323                 #size-cells = <0>;
324                 clock-frequency = <80000>;
325                 request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
326                 slave-addr = <138>;
327                 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
328                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
329                 clock-names = "div-clk", "fast-clk";
330                 resets = <&tegra_car 67>;
331                 reset-names = "i2c";
332         };
333
334         i2c@7000d000 {
335                 status = "okay";
336                 clock-frequency = <400000>;
337
338                 pmic: tps6586x@34 {
339                         compatible = "ti,tps6586x";
340                         reg = <0x34>;
341                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
342
343                         #gpio-cells = <2>;
344                         gpio-controller;
345
346                         sys-supply = <&p5valw_reg>;
347                         vin-sm0-supply = <&sys_reg>;
348                         vin-sm1-supply = <&sys_reg>;
349                         vin-sm2-supply = <&sys_reg>;
350                         vinldo01-supply = <&sm2_reg>;
351                         vinldo23-supply = <&sm2_reg>;
352                         vinldo4-supply = <&sm2_reg>;
353                         vinldo678-supply = <&sm2_reg>;
354                         vinldo9-supply = <&sm2_reg>;
355
356                         regulators {
357                                 sys_reg: sys {
358                                         regulator-name = "vdd_sys";
359                                         regulator-always-on;
360                                 };
361
362                                 sm0 {
363                                         regulator-name = "+1.2vs_sm0,vdd_core";
364                                         regulator-min-microvolt = <1200000>;
365                                         regulator-max-microvolt = <1200000>;
366                                         regulator-always-on;
367                                 };
368
369                                 sm1 {
370                                         regulator-name = "+1.0vs_sm1,vdd_cpu";
371                                         regulator-min-microvolt = <1000000>;
372                                         regulator-max-microvolt = <1000000>;
373                                         regulator-always-on;
374                                 };
375
376                                 sm2_reg: sm2 {
377                                         regulator-name = "+3.7vs_sm2,vin_ldo*";
378                                         regulator-min-microvolt = <3700000>;
379                                         regulator-max-microvolt = <3700000>;
380                                         regulator-always-on;
381                                 };
382
383                                 /* LDO0 is not connected to anything */
384
385                                 ldo1 {
386                                         regulator-name = "+1.1vs_ldo1,avdd_pll*";
387                                         regulator-min-microvolt = <1100000>;
388                                         regulator-max-microvolt = <1100000>;
389                                         regulator-always-on;
390                                 };
391
392                                 ldo2 {
393                                         regulator-name = "+1.2vs_ldo2,vdd_rtc";
394                                         regulator-min-microvolt = <1200000>;
395                                         regulator-max-microvolt = <1200000>;
396                                 };
397
398                                 ldo3 {
399                                         regulator-name = "+3.3vs_ldo3,avdd_usb*";
400                                         regulator-min-microvolt = <3300000>;
401                                         regulator-max-microvolt = <3300000>;
402                                         regulator-always-on;
403                                 };
404
405                                 ldo4 {
406                                         regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
407                                         regulator-min-microvolt = <1800000>;
408                                         regulator-max-microvolt = <1800000>;
409                                         regulator-always-on;
410                                 };
411
412                                 ldo5 {
413                                         regulator-name = "+2.85vs_ldo5,vcore_mmc";
414                                         regulator-min-microvolt = <2850000>;
415                                         regulator-max-microvolt = <2850000>;
416                                         regulator-always-on;
417                                 };
418
419                                 ldo6 {
420                                         /*
421                                          * Research indicates this should be
422                                          * 1.8v; other boards that use this
423                                          * rail for the same purpose need it
424                                          * set to 1.8v. The schematic signal
425                                          * name is incorrect; perhaps copied
426                                          * from an incorrect NVIDIA reference.
427                                          */
428                                         regulator-name = "+2.85vs_ldo6,avdd_vdac";
429                                         regulator-min-microvolt = <1800000>;
430                                         regulator-max-microvolt = <1800000>;
431                                 };
432
433                                 hdmi_vdd_reg: ldo7 {
434                                         regulator-name = "+3.3vs_ldo7,avdd_hdmi";
435                                         regulator-min-microvolt = <3300000>;
436                                         regulator-max-microvolt = <3300000>;
437                                 };
438
439                                 hdmi_pll_reg: ldo8 {
440                                         regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
441                                         regulator-min-microvolt = <1800000>;
442                                         regulator-max-microvolt = <1800000>;
443                                 };
444
445                                 ldo9 {
446                                         regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
447                                         regulator-min-microvolt = <2850000>;
448                                         regulator-max-microvolt = <2850000>;
449                                         regulator-always-on;
450                                 };
451
452                                 ldo_rtc {
453                                         regulator-name = "+3.3vs_rtc";
454                                         regulator-min-microvolt = <3300000>;
455                                         regulator-max-microvolt = <3300000>;
456                                         regulator-always-on;
457                                 };
458                         };
459                 };
460
461                 adt7461@4c {
462                         compatible = "adi,adt7461";
463                         reg = <0x4c>;
464                 };
465         };
466
467         pmc@7000e400 {
468                 nvidia,invert-interrupt;
469                 nvidia,suspend-mode = <1>;
470                 nvidia,cpu-pwr-good-time = <2000>;
471                 nvidia,cpu-pwr-off-time = <0>;
472                 nvidia,core-pwr-good-time = <3845 3845>;
473                 nvidia,core-pwr-off-time = <0>;
474                 nvidia,sys-clock-req-active-high;
475         };
476
477         usb@c5000000 {
478                 status = "okay";
479         };
480
481         usb-phy@c5000000 {
482                 status = "okay";
483         };
484
485         usb@c5004000 {
486                 status = "okay";
487                 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
488                         GPIO_ACTIVE_LOW>;
489         };
490
491         usb-phy@c5004000 {
492                 status = "okay";
493                 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
494                         GPIO_ACTIVE_LOW>;
495         };
496
497         usb@c5008000 {
498                 status = "okay";
499         };
500
501         usb-phy@c5008000 {
502                 status = "okay";
503         };
504
505         sdhci@c8000000 {
506                 status = "okay";
507                 cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
508                 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
509                 power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
510                 bus-width = <4>;
511         };
512
513         sdhci@c8000600 {
514                 status = "okay";
515                 bus-width = <8>;
516                 non-removable;
517         };
518
519         backlight: backlight {
520                 compatible = "pwm-backlight";
521
522                 enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
523                 power-supply = <&vdd_bl_reg>;
524                 pwms = <&pwm 0 5000000>;
525
526                 brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>;
527                 default-brightness-level = <10>;
528
529                 backlight-boot-off;
530         };
531
532         clocks {
533                 compatible = "simple-bus";
534                 #address-cells = <1>;
535                 #size-cells = <0>;
536
537                 clk32k_in: clock@0 {
538                         compatible = "fixed-clock";
539                         reg = <0>;
540                         #clock-cells = <0>;
541                         clock-frequency = <32768>;
542                 };
543         };
544
545         gpio-keys {
546                 compatible = "gpio-keys";
547
548                 power {
549                         label = "Power";
550                         gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
551                         linux,code = <KEY_POWER>;
552                         wakeup-source;
553                 };
554         };
555
556         gpio-leds {
557                 compatible = "gpio-leds";
558
559                 wifi {
560                         label = "wifi-led";
561                         gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
562                         linux,default-trigger = "rfkill0";
563                 };
564         };
565
566         panel: panel {
567                 compatible = "samsung,ltn101nt05", "simple-panel";
568
569                 ddc-i2c-bus = <&lvds_ddc>;
570                 power-supply = <&vdd_pnl_reg>;
571                 enable-gpios = <&gpio TEGRA_GPIO(M, 6) GPIO_ACTIVE_HIGH>;
572
573                 backlight = <&backlight>;
574         };
575
576         regulators {
577                 compatible = "simple-bus";
578                 #address-cells = <1>;
579                 #size-cells = <0>;
580
581                 p5valw_reg: regulator@0 {
582                         compatible = "regulator-fixed";
583                         reg = <0>;
584                         regulator-name = "+5valw";
585                         regulator-min-microvolt = <5000000>;
586                         regulator-max-microvolt = <5000000>;
587                         regulator-always-on;
588                 };
589
590                 vdd_pnl_reg: regulator@1 {
591                         compatible = "regulator-fixed";
592                         reg = <1>;
593                         regulator-name = "+3VS,vdd_pnl";
594                         regulator-min-microvolt = <3300000>;
595                         regulator-max-microvolt = <3300000>;
596                         gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>;
597                         enable-active-high;
598                 };
599
600                 vdd_bl_reg: regulator@2 {
601                         compatible = "regulator-fixed";
602                         reg = <2>;
603                         regulator-name = "vdd_bl";
604                         regulator-min-microvolt = <2800000>;
605                         regulator-max-microvolt = <2800000>;
606                         gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
607                         enable-active-high;
608                 };
609         };
610
611         sound {
612                 compatible = "nvidia,tegra-audio-alc5632-paz00",
613                         "nvidia,tegra-audio-alc5632";
614
615                 nvidia,model = "Compal PAZ00";
616
617                 nvidia,audio-routing =
618                         "Int Spk", "SPKOUT",
619                         "Int Spk", "SPKOUTN",
620                         "Headset Mic", "MICBIAS1",
621                         "MIC1", "Headset Mic",
622                         "Headset Stereophone", "HPR",
623                         "Headset Stereophone", "HPL",
624                         "DMICDAT", "Digital Mic";
625
626                 nvidia,audio-codec = <&alc5632>;
627                 nvidia,i2s-controller = <&tegra_i2s1>;
628                 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
629                         GPIO_ACTIVE_HIGH>;
630
631                 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
632                          <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
633                          <&tegra_car TEGRA20_CLK_CDEV1>;
634                 clock-names = "pll_a", "pll_a_out0", "mclk";
635         };
636 };