arch/arm/dts/tegra186.dtsi

   1 #include "skeleton.dtsi"
   2 #include <dt-bindings/gpio/tegra186-gpio.h>
   3 #include <dt-bindings/interrupt-controller/arm-gic.h>
   4 #include <dt-bindings/mailbox/tegra-hsp.h>
   5
   6 / {
   7         compatible = "nvidia,tegra186";
   8         #address-cells = <2>;
   9         #size-cells = <2>;
  10
  11         gpio@2200000 {
  12                 compatible = "nvidia,tegra186-gpio";
  13                 reg-names = "security", "gpio";
  14                 reg =
  15                         <0x0 0x2200000 0x0 0x10000>,
  16                         <0x0 0x2210000 0x0 0x10000>;
  17                 interrupts =
  18                         <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
  19                         <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
  20                         <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
  21                         <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
  22                         <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
  23                         <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
  24                 gpio-controller;
  25                 #gpio-cells = <2>;
  26                 interrupt-controller;
  27                 #interrupt-cells = <2>;
  28         };
  29
  30         uarta: serial@3100000 {
  31                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
  32                 reg = <0x0 0x03100000 0x0 0x10000>;
  33                 reg-shift = <2>;
  34                 status = "disabled";
  35         };
  36
  37         sdhci@3460000 {
  38                 compatible = "nvidia,tegra186-sdhci";
  39                 reg = <0x0 0x03460000 0x0 0x200>;
  40                 interrupts = <GIC_SPI 31 0x04>;
  41                 status = "disabled";
  42         };
  43
  44         hsp: hsp@3c00000 {
  45                 compatible = "nvidia,tegra186-hsp";
  46                 reg = <0x0 0x03c00000 0x0 0xa0000>;
  47                 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
  48                 nvidia,num-SM = <0x8>;
  49                 nvidia,num-AS = <0x2>;
  50                 nvidia,num-SS = <0x2>;
  51                 nvidia,num-DB = <0x7>;
  52                 nvidia,num-SI = <0x8>;
  53                 #mbox-cells = <1>;
  54         };
  55
  56         gpio@c2f0000 {
  57                 compatible = "nvidia,tegra186-gpio-aon";
  58                 reg-names = "security", "gpio";
  59                 reg =
  60                         <0x0 0xc2f0000 0x0 0x1000>,
  61                         <0x0 0xc2f1000 0x0 0x1000>;
  62                 interrupts =
  63                         <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
  64                 gpio-controller;
  65                 #gpio-cells = <2>;
  66                 interrupt-controller;
  67                 #interrupt-cells = <2>;
  68         };
  69 };