arch/arm/dts/tegra124.dtsi

   1 #include <dt-bindings/clock/tegra124-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
   6
   7 #include "skeleton.dtsi"
   8
   9 / {
  10         compatible = "nvidia,tegra124";
  11         interrupt-parent = <&gic>;
  12
  13         gic: interrupt-controller@50041000 {
  14                 compatible = "arm,cortex-a15-gic";
  15                 #interrupt-cells = <3>;
  16                 interrupt-controller;
  17                 reg = <0x50041000 0x1000>,
  18                       <0x50042000 0x2000>,
  19                       <0x50044000 0x2000>,
  20                       <0x50046000 0x2000>;
  21                 interrupts = <GIC_PPI 9
  22                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  23         };
  24
  25         tegra_car: clock@60006000 {
  26                 compatible = "nvidia,tegra124-car";
  27                 reg = <0x60006000 0x1000>;
  28                 #clock-cells = <1>;
  29         };
  30
  31         apbdma: dma@60020000 {
  32                 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
  33                 reg = <0x60020000 0x1400>;
  34                 interrupts = <0 104 0x04
  35                               0 105 0x04
  36                               0 106 0x04
  37                               0 107 0x04
  38                               0 108 0x04
  39                               0 109 0x04
  40                               0 110 0x04
  41                               0 111 0x04
  42                               0 112 0x04
  43                               0 113 0x04
  44                               0 114 0x04
  45                               0 115 0x04
  46                               0 116 0x04
  47                               0 117 0x04
  48                               0 118 0x04
  49                               0 119 0x04
  50                               0 128 0x04
  51                               0 129 0x04
  52                               0 130 0x04
  53                               0 131 0x04
  54                               0 132 0x04
  55                               0 133 0x04
  56                               0 134 0x04
  57                               0 135 0x04
  58                               0 136 0x04
  59                               0 137 0x04
  60                               0 138 0x04
  61                               0 139 0x04
  62                               0 140 0x04
  63                               0 141 0x04
  64                               0 142 0x04
  65                               0 143 0x04>;
  66         };
  67
  68         gpio: gpio@6000d000 {
  69                 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
  70                 reg = <0x6000d000 0x1000>;
  71                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
  72                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
  73                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
  74                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
  75                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
  76                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
  77                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
  78                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
  79                 #gpio-cells = <2>;
  80                 gpio-controller;
  81                 #interrupt-cells = <2>;
  82                 interrupt-controller;
  83         };
  84
  85         i2c@7000c000 {
  86                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
  87                 reg = <0x7000c000 0x100>;
  88                 interrupts = <0 38 0x04>;
  89                 #address-cells = <1>;
  90                 #size-cells = <0>;
  91                 clocks = <&tegra_car 12>;
  92                 status = "disabled";
  93         };
  94
  95         i2c@7000c400 {
  96                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
  97                 reg = <0x7000c400 0x100>;
  98                 interrupts = <0 84 0x04>;
  99                 #address-cells = <1>;
 100                 #size-cells = <0>;
 101                 clocks = <&tegra_car 54>;
 102                 status = "disabled";
 103         };
 104
 105         i2c@7000c500 {
 106                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 107                 reg = <0x7000c500 0x100>;
 108                 interrupts = <0 92 0x04>;
 109                 #address-cells = <1>;
 110                 #size-cells = <0>;
 111                 clocks = <&tegra_car 67>;
 112                 status = "disabled";
 113         };
 114
 115         i2c@7000c700 {
 116                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 117                 reg = <0x7000c700 0x100>;
 118                 interrupts = <0 120 0x04>;
 119                 #address-cells = <1>;
 120                 #size-cells = <0>;
 121                 clocks = <&tegra_car 103>;
 122                 status = "disabled";
 123         };
 124
 125         i2c@7000d000 {
 126                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 127                 reg = <0x7000d000 0x100>;
 128                 interrupts = <0 53 0x04>;
 129                 #address-cells = <1>;
 130                 #size-cells = <0>;
 131                 clocks = <&tegra_car 47>;
 132                 status = "disabled";
 133         };
 134
 135         i2c@7000d100 {
 136                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 137                 reg = <0x7000d100 0x100>;
 138                 interrupts = <0 53 0x04>;
 139                 #address-cells = <1>;
 140                 #size-cells = <0>;
 141                 clocks = <&tegra_car 47>;
 142                 status = "disabled";
 143         };
 144
 145         uarta: serial@70006000 {
 146                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 147                 reg = <0x70006000 0x40>;
 148                 reg-shift = <2>;
 149                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 150                 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
 151                 resets = <&tegra_car 6>;
 152                 reset-names = "serial";
 153                 dmas = <&apbdma 8>, <&apbdma 8>;
 154                 dma-names = "rx", "tx";
 155                 status = "disabled";
 156         };
 157
 158         uartb: serial@70006040 {
 159                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 160                 reg = <0x70006040 0x40>;
 161                 reg-shift = <2>;
 162                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 163                 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
 164                 resets = <&tegra_car 7>;
 165                 reset-names = "serial";
 166                 dmas = <&apbdma 9>, <&apbdma 9>;
 167                 dma-names = "rx", "tx";
 168                 status = "disabled";
 169         };
 170
 171         uartc: serial@70006200 {
 172                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 173                 reg = <0x70006200 0x40>;
 174                 reg-shift = <2>;
 175                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 176                 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
 177                 resets = <&tegra_car 55>;
 178                 reset-names = "serial";
 179                 dmas = <&apbdma 10>, <&apbdma 10>;
 180                 dma-names = "rx", "tx";
 181                 status = "disabled";
 182         };
 183
 184         uartd: serial@70006300 {
 185                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 186                 reg = <0x70006300 0x40>;
 187                 reg-shift = <2>;
 188                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 189                 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
 190                 resets = <&tegra_car 65>;
 191                 reset-names = "serial";
 192                 dmas = <&apbdma 19>, <&apbdma 19>;
 193                 dma-names = "rx", "tx";
 194                 status = "disabled";
 195         };
 196
 197         uarte: serial@70006400 {
 198                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 199                 reg = <0x70006400 0x40>;
 200                 reg-shift = <2>;
 201                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 202                 clocks = <&tegra_car TEGRA124_CLK_UARTE>;
 203                 resets = <&tegra_car 66>;
 204                 reset-names = "serial";
 205                 dmas = <&apbdma 20>, <&apbdma 20>;
 206                 dma-names = "rx", "tx";
 207                 status = "disabled";
 208         };
 209
 210         pwm: pwm@7000a000 {
 211                 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
 212                 reg = <0x7000a000 0x100>;
 213                 #pwm-cells = <2>;
 214                 clocks = <&tegra_car TEGRA124_CLK_PWM>;
 215                 resets = <&tegra_car 17>;
 216                 reset-names = "pwm";
 217                 status = "disabled";
 218         };
 219
 220         spi@7000d400 {
 221                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 222                 reg = <0x7000d400 0x200>;
 223                 interrupts = <0 59 0x04>;
 224                 nvidia,dma-request-selector = <&apbdma 15>;
 225                 #address-cells = <1>;
 226                 #size-cells = <0>;
 227                 status = "disabled";
 228                 clocks = <&tegra_car 41>;
 229         };
 230
 231         spi@7000d600 {
 232                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 233                 reg = <0x7000d600 0x200>;
 234                 interrupts = <0 82 0x04>;
 235                 nvidia,dma-request-selector = <&apbdma 16>;
 236                 #address-cells = <1>;
 237                 #size-cells = <0>;
 238                 status = "disabled";
 239                 clocks = <&tegra_car 44>;
 240         };
 241
 242         spi@7000d800 {
 243                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 244                 reg = <0x7000d800 0x200>;
 245                 interrupts = <0 83 0x04>;
 246                 nvidia,dma-request-selector = <&apbdma 17>;
 247                 #address-cells = <1>;
 248                 #size-cells = <0>;
 249                 status = "disabled";
 250                 clocks = <&tegra_car 46>;
 251         };
 252
 253         spi@7000da00 {
 254                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 255                 reg = <0x7000da00 0x200>;
 256                 interrupts = <0 93 0x04>;
 257                 nvidia,dma-request-selector = <&apbdma 18>;
 258                 #address-cells = <1>;
 259                 #size-cells = <0>;
 260                 status = "disabled";
 261                 clocks = <&tegra_car 68>;
 262         };
 263
 264         spi@7000dc00 {
 265                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 266                 reg = <0x7000dc00 0x200>;
 267                 interrupts = <0 94 0x04>;
 268                 nvidia,dma-request-selector = <&apbdma 27>;
 269                 #address-cells = <1>;
 270                 #size-cells = <0>;
 271                 status = "disabled";
 272                 clocks = <&tegra_car 104>;
 273         };
 274
 275         spi@7000de00 {
 276                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 277                 reg = <0x7000de00 0x200>;
 278                 interrupts = <0 79 0x04>;
 279                 nvidia,dma-request-selector = <&apbdma 28>;
 280                 #address-cells = <1>;
 281                 #size-cells = <0>;
 282                 status = "disabled";
 283                 clocks = <&tegra_car 105>;
 284         };
 285
 286         padctl: padctl@7009f000 {
 287                 compatible = "nvidia,tegra124-xusb-padctl";
 288                 reg = <0x7009f000 0x1000>;
 289                 resets = <&tegra_car 142>;
 290                 reset-names = "padctl";
 291
 292                 #phy-cells = <1>;
 293         };
 294
 295         sdhci@700b0000 {
 296                 compatible = "nvidia,tegra124-sdhci";
 297                 reg = <0x700b0000 0x200>;
 298                 interrupts = <0 14 0x04>;
 299                 clocks = <&tegra_car 14>;
 300                 status = "disabled";
 301         };
 302
 303         sdhci@700b0200 {
 304                 compatible = "nvidia,tegra124-sdhci";
 305                 reg = <0x700b0200 0x200>;
 306                 interrupts = <0 15 0x04>;
 307                 clocks = <&tegra_car 9>;
 308                 status = "disabled";
 309         };
 310
 311         sdhci@700b0400 {
 312                 compatible = "nvidia,tegra124-sdhci";
 313                 reg = <0x700b0400 0x200>;
 314                 interrupts = <0 19 0x04>;
 315                 clocks = <&tegra_car 69>;
 316                 status = "disabled";
 317         };
 318
 319         sdhci@700b0600 {
 320                 compatible = "nvidia,tegra124-sdhci";
 321                 reg = <0x700b0600 0x200>;
 322                 interrupts = <0 31 0x04>;
 323                 clocks = <&tegra_car 15>;
 324                 status = "disabled";
 325         };
 326
 327         ahub@70300000 {
 328                 compatible = "nvidia,tegra124-ahub";
 329                 reg = <0x70300000 0x200>,
 330                       <0x70300800 0x800>,
 331                       <0x70300200 0x600>;
 332                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 333                 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
 334                          <&tegra_car TEGRA124_CLK_APBIF>;
 335                 clock-names = "d_audio", "apbif";
 336                 resets = <&tegra_car 106>, /* d_audio */
 337                          <&tegra_car 107>, /* apbif */
 338                          <&tegra_car 30>,  /* i2s0 */
 339                          <&tegra_car 11>,  /* i2s1 */
 340                          <&tegra_car 18>,  /* i2s2 */
 341                          <&tegra_car 101>, /* i2s3 */
 342                          <&tegra_car 102>, /* i2s4 */
 343                          <&tegra_car 108>, /* dam0 */
 344                          <&tegra_car 109>, /* dam1 */
 345                          <&tegra_car 110>, /* dam2 */
 346                          <&tegra_car 10>,  /* spdif */
 347                          <&tegra_car 153>, /* amx */
 348                          <&tegra_car 185>, /* amx1 */
 349                          <&tegra_car 154>, /* adx */
 350                          <&tegra_car 180>, /* adx1 */
 351                          <&tegra_car 186>, /* afc0 */
 352                          <&tegra_car 187>, /* afc1 */
 353                          <&tegra_car 188>, /* afc2 */
 354                          <&tegra_car 189>, /* afc3 */
 355                          <&tegra_car 190>, /* afc4 */
 356                          <&tegra_car 191>; /* afc5 */
 357                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 358                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 359                               "spdif", "amx", "amx1", "adx", "adx1",
 360                               "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
 361                 dmas = <&apbdma 1>, <&apbdma 1>,
 362                        <&apbdma 2>, <&apbdma 2>,
 363                        <&apbdma 3>, <&apbdma 3>,
 364                        <&apbdma 4>, <&apbdma 4>,
 365                        <&apbdma 6>, <&apbdma 6>,
 366                        <&apbdma 7>, <&apbdma 7>,
 367                        <&apbdma 12>, <&apbdma 12>,
 368                        <&apbdma 13>, <&apbdma 13>,
 369                        <&apbdma 14>, <&apbdma 14>,
 370                        <&apbdma 29>, <&apbdma 29>;
 371                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 372                             "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
 373                             "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
 374                             "rx9", "tx9";
 375                 ranges;
 376                 #address-cells = <1>;
 377                 #size-cells = <1>;
 378
 379                 tegra_i2s0: i2s@70301000 {
 380                         compatible = "nvidia,tegra124-i2s";
 381                         reg = <0x70301000 0x100>;
 382                         nvidia,ahub-cif-ids = <4 4>;
 383                         clocks = <&tegra_car TEGRA124_CLK_I2S0>;
 384                         resets = <&tegra_car 30>;
 385                         reset-names = "i2s";
 386                         status = "disabled";
 387                 };
 388
 389                 tegra_i2s1: i2s@70301100 {
 390                         compatible = "nvidia,tegra124-i2s";
 391                         reg = <0x70301100 0x100>;
 392                         nvidia,ahub-cif-ids = <5 5>;
 393                         clocks = <&tegra_car TEGRA124_CLK_I2S1>;
 394                         resets = <&tegra_car 11>;
 395                         reset-names = "i2s";
 396                         status = "disabled";
 397                 };
 398
 399                 tegra_i2s2: i2s@70301200 {
 400                         compatible = "nvidia,tegra124-i2s";
 401                         reg = <0x70301200 0x100>;
 402                         nvidia,ahub-cif-ids = <6 6>;
 403                         clocks = <&tegra_car TEGRA124_CLK_I2S2>;
 404                         resets = <&tegra_car 18>;
 405                         reset-names = "i2s";
 406                         status = "disabled";
 407                 };
 408
 409                 tegra_i2s3: i2s@70301300 {
 410                         compatible = "nvidia,tegra124-i2s";
 411                         reg = <0x70301300 0x100>;
 412                         nvidia,ahub-cif-ids = <7 7>;
 413                         clocks = <&tegra_car TEGRA124_CLK_I2S3>;
 414                         resets = <&tegra_car 101>;
 415                         reset-names = "i2s";
 416                         status = "disabled";
 417                 };
 418
 419                 tegra_i2s4: i2s@70301400 {
 420                         compatible = "nvidia,tegra124-i2s";
 421                         reg = <0x70301400 0x100>;
 422                         nvidia,ahub-cif-ids = <8 8>;
 423                         clocks = <&tegra_car TEGRA124_CLK_I2S4>;
 424                         resets = <&tegra_car 102>;
 425                         reset-names = "i2s";
 426                         status = "disabled";
 427                 };
 428         };
 429
 430         usb@7d000000 {
 431                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
 432                 reg = <0x7d000000 0x4000>;
 433                 interrupts = < 52 >;
 434                 phy_type = "utmi";
 435                 clocks = <&tegra_car 22>;       /* PERIPH_ID_USBD */
 436                 status = "disabled";
 437         };
 438
 439         usb@7d004000 {
 440                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
 441                 reg = <0x7d004000 0x4000>;
 442                 interrupts = < 53 >;
 443                 phy_type = "hsic";
 444                 clocks = <&tegra_car 58>;       /* PERIPH_ID_USB2 */
 445                 status = "disabled";
 446         };
 447
 448         usb@7d008000 {
 449                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
 450                 reg = <0x7d008000 0x4000>;
 451                 interrupts = < 129 >;
 452                 phy_type = "utmi";
 453                 clocks = <&tegra_car 59>;       /* PERIPH_ID_USB3 */
 454                 status = "disabled";
 455         };
 456 };