arch/arm/dts/sun9i-a80.dtsi

   1 /*
   2  * Copyright 2014 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "skeleton64.dtsi"
  46
  47 #include <dt-bindings/interrupt-controller/arm-gic.h>
  48
  49 #include <dt-bindings/pinctrl/sun4i-a10.h>
  50
  51 / {
  52         interrupt-parent = <&gic>;
  53
  54         cpus {
  55                 #address-cells = <1>;
  56                 #size-cells = <0>;
  57
  58                 cpu0: cpu@0 {
  59                         compatible = "arm,cortex-a7";
  60                         device_type = "cpu";
  61                         reg = <0x0>;
  62                 };
  63
  64                 cpu1: cpu@1 {
  65                         compatible = "arm,cortex-a7";
  66                         device_type = "cpu";
  67                         reg = <0x1>;
  68                 };
  69
  70                 cpu2: cpu@2 {
  71                         compatible = "arm,cortex-a7";
  72                         device_type = "cpu";
  73                         reg = <0x2>;
  74                 };
  75
  76                 cpu3: cpu@3 {
  77                         compatible = "arm,cortex-a7";
  78                         device_type = "cpu";
  79                         reg = <0x3>;
  80                 };
  81
  82                 cpu4: cpu@100 {
  83                         compatible = "arm,cortex-a15";
  84                         device_type = "cpu";
  85                         reg = <0x100>;
  86                 };
  87
  88                 cpu5: cpu@101 {
  89                         compatible = "arm,cortex-a15";
  90                         device_type = "cpu";
  91                         reg = <0x101>;
  92                 };
  93
  94                 cpu6: cpu@102 {
  95                         compatible = "arm,cortex-a15";
  96                         device_type = "cpu";
  97                         reg = <0x102>;
  98                 };
  99
 100                 cpu7: cpu@103 {
 101                         compatible = "arm,cortex-a15";
 102                         device_type = "cpu";
 103                         reg = <0x103>;
 104                 };
 105         };
 106
 107         memory {
 108                 /* 8GB max. with LPAE */
 109                 reg = <0 0x20000000 0x02 0>;
 110         };
 111
 112         timer {
 113                 compatible = "arm,armv7-timer";
 114                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 115                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 116                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 117                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 118                 clock-frequency = <24000000>;
 119                 arm,cpu-registers-not-fw-configured;
 120         };
 121
 122         clocks {
 123                 #address-cells = <1>;
 124                 #size-cells = <1>;
 125                 /*
 126                  * map 64 bit address range down to 32 bits,
 127                  * as the peripherals are all under 512MB.
 128                  */
 129                 ranges = <0 0 0 0x20000000>;
 130
 131                 /*
 132                  * This clock is actually configurable from the PRCM address
 133                  * space. The external 24M oscillator can be turned off, and
 134                  * the clock switched to an internal 16M RC oscillator. Under
 135                  * normal operation there's no reason to do this, and the
 136                  * default is to use the external good one, so just model this
 137                  * as a fixed clock. Also it is not entirely clear if the
 138                  * osc24M mux in the PRCM affects the entire clock tree, which
 139                  * would also throw all the PLL clock rates off, or just the
 140                  * downstream clocks in the PRCM.
 141                  */
 142                 osc24M: osc24M_clk {
 143                         #clock-cells = <0>;
 144                         compatible = "fixed-clock";
 145                         clock-frequency = <24000000>;
 146                         clock-output-names = "osc24M";
 147                 };
 148
 149                 /*
 150                  * The 32k clock is from an external source, normally the
 151                  * AC100 codec/RTC chip. This clock is by default enabled
 152                  * and clocked at 32768 Hz, from the oscillator connected
 153                  * to the AC100. It is configurable, but no such driver or
 154                  * bindings exist yet.
 155                  */
 156                 osc32k: osc32k_clk {
 157                         #clock-cells = <0>;
 158                         compatible = "fixed-clock";
 159                         clock-frequency = <32768>;
 160                         clock-output-names = "osc32k";
 161                 };
 162
 163                 usb_mod_clk: clk@00a08000 {
 164                         #clock-cells = <1>;
 165                         #reset-cells = <1>;
 166                         compatible = "allwinner,sun9i-a80-usb-mod-clk";
 167                         reg = <0x00a08000 0x4>;
 168                         clocks = <&ahb1_gates 1>;
 169                         clock-output-names = "usb0_ahb", "usb_ohci0",
 170                                              "usb1_ahb", "usb_ohci1",
 171                                              "usb2_ahb", "usb_ohci2";
 172                 };
 173
 174                 usb_phy_clk: clk@00a08004 {
 175                         #clock-cells = <1>;
 176                         #reset-cells = <1>;
 177                         compatible = "allwinner,sun9i-a80-usb-phy-clk";
 178                         reg = <0x00a08004 0x4>;
 179                         clocks = <&ahb1_gates 1>;
 180                         clock-output-names = "usb_phy0", "usb_hsic1_480M",
 181                                              "usb_phy1", "usb_hsic2_480M",
 182                                              "usb_phy2", "usb_hsic_12M";
 183                 };
 184
 185                 pll3: clk@06000008 {
 186                         /* placeholder until implemented */
 187                         #clock-cells = <0>;
 188                         compatible = "fixed-clock";
 189                         clock-rate = <0>;
 190                         clock-output-names = "pll3";
 191                 };
 192
 193                 pll4: clk@0600000c {
 194                         #clock-cells = <0>;
 195                         compatible = "allwinner,sun9i-a80-pll4-clk";
 196                         reg = <0x0600000c 0x4>;
 197                         clocks = <&osc24M>;
 198                         clock-output-names = "pll4";
 199                 };
 200
 201                 pll12: clk@0600002c {
 202                         #clock-cells = <0>;
 203                         compatible = "allwinner,sun9i-a80-pll4-clk";
 204                         reg = <0x0600002c 0x4>;
 205                         clocks = <&osc24M>;
 206                         clock-output-names = "pll12";
 207                 };
 208
 209                 gt_clk: clk@0600005c {
 210                         #clock-cells = <0>;
 211                         compatible = "allwinner,sun9i-a80-gt-clk";
 212                         reg = <0x0600005c 0x4>;
 213                         clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
 214                         clock-output-names = "gt";
 215                 };
 216
 217                 ahb0: clk@06000060 {
 218                         #clock-cells = <0>;
 219                         compatible = "allwinner,sun9i-a80-ahb-clk";
 220                         reg = <0x06000060 0x4>;
 221                         clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
 222                         clock-output-names = "ahb0";
 223                 };
 224
 225                 ahb1: clk@06000064 {
 226                         #clock-cells = <0>;
 227                         compatible = "allwinner,sun9i-a80-ahb-clk";
 228                         reg = <0x06000064 0x4>;
 229                         clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
 230                         clock-output-names = "ahb1";
 231                 };
 232
 233                 ahb2: clk@06000068 {
 234                         #clock-cells = <0>;
 235                         compatible = "allwinner,sun9i-a80-ahb-clk";
 236                         reg = <0x06000068 0x4>;
 237                         clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
 238                         clock-output-names = "ahb2";
 239                 };
 240
 241                 apb0: clk@06000070 {
 242                         #clock-cells = <0>;
 243                         compatible = "allwinner,sun9i-a80-apb0-clk";
 244                         reg = <0x06000070 0x4>;
 245                         clocks = <&osc24M>, <&pll4>;
 246                         clock-output-names = "apb0";
 247                 };
 248
 249                 apb1: clk@06000074 {
 250                         #clock-cells = <0>;
 251                         compatible = "allwinner,sun9i-a80-apb1-clk";
 252                         reg = <0x06000074 0x4>;
 253                         clocks = <&osc24M>, <&pll4>;
 254                         clock-output-names = "apb1";
 255                 };
 256
 257                 cci400_clk: clk@06000078 {
 258                         #clock-cells = <0>;
 259                         compatible = "allwinner,sun9i-a80-gt-clk";
 260                         reg = <0x06000078 0x4>;
 261                         clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
 262                         clock-output-names = "cci400";
 263                 };
 264
 265                 mmc0_clk: clk@06000410 {
 266                         #clock-cells = <1>;
 267                         compatible = "allwinner,sun9i-a80-mmc-clk";
 268                         reg = <0x06000410 0x4>;
 269                         clocks = <&osc24M>, <&pll4>;
 270                         clock-output-names = "mmc0", "mmc0_output",
 271                                              "mmc0_sample";
 272                 };
 273
 274                 mmc1_clk: clk@06000414 {
 275                         #clock-cells = <1>;
 276                         compatible = "allwinner,sun9i-a80-mmc-clk";
 277                         reg = <0x06000414 0x4>;
 278                         clocks = <&osc24M>, <&pll4>;
 279                         clock-output-names = "mmc1", "mmc1_output",
 280                                              "mmc1_sample";
 281                 };
 282
 283                 mmc2_clk: clk@06000418 {
 284                         #clock-cells = <1>;
 285                         compatible = "allwinner,sun9i-a80-mmc-clk";
 286                         reg = <0x06000418 0x4>;
 287                         clocks = <&osc24M>, <&pll4>;
 288                         clock-output-names = "mmc2", "mmc2_output",
 289                                              "mmc2_sample";
 290                 };
 291
 292                 mmc3_clk: clk@0600041c {
 293                         #clock-cells = <1>;
 294                         compatible = "allwinner,sun9i-a80-mmc-clk";
 295                         reg = <0x0600041c 0x4>;
 296                         clocks = <&osc24M>, <&pll4>;
 297                         clock-output-names = "mmc3", "mmc3_output",
 298                                              "mmc3_sample";
 299                 };
 300
 301                 ahb0_gates: clk@06000580 {
 302                         #clock-cells = <1>;
 303                         compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
 304                         reg = <0x06000580 0x4>;
 305                         clocks = <&ahb0>;
 306                         clock-indices = <0>, <1>, <3>,
 307                                         <5>, <8>, <12>,
 308                                         <13>, <14>,
 309                                         <15>, <16>, <18>,
 310                                         <20>, <21>, <22>,
 311                                         <23>;
 312                         clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
 313                                         "ahb0_ss", "ahb0_sd", "ahb0_nand1",
 314                                         "ahb0_nand0", "ahb0_sdram",
 315                                         "ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts",
 316                                         "ahb0_spi0", "ahb0_spi1", "ahb0_spi2",
 317                                         "ahb0_spi3";
 318                 };
 319
 320                 ahb1_gates: clk@06000584 {
 321                         #clock-cells = <1>;
 322                         compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
 323                         reg = <0x06000584 0x4>;
 324                         clocks = <&ahb1>;
 325                         clock-indices = <0>, <1>,
 326                                         <17>, <21>,
 327                                         <22>, <23>,
 328                                         <24>;
 329                         clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
 330                                         "ahb1_gmac", "ahb1_msgbox",
 331                                         "ahb1_spinlock", "ahb1_hstimer",
 332                                         "ahb1_dma";
 333                 };
 334
 335                 ahb2_gates: clk@06000588 {
 336                         #clock-cells = <1>;
 337                         compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
 338                         reg = <0x06000588 0x4>;
 339                         clocks = <&ahb2>;
 340                         clock-indices = <0>, <1>,
 341                                         <2>, <4>, <5>,
 342                                         <7>, <8>, <11>;
 343                         clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
 344                                         "ahb2_edp", "ahb2_csi", "ahb2_hdmi",
 345                                         "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
 346                 };
 347
 348                 apb0_gates: clk@06000590 {
 349                         #clock-cells = <1>;
 350                         compatible = "allwinner,sun9i-a80-apb0-gates-clk";
 351                         reg = <0x06000590 0x4>;
 352                         clocks = <&apb0>;
 353                         clock-indices = <1>, <5>,
 354                                         <11>, <12>, <13>,
 355                                         <15>, <17>, <18>,
 356                                         <19>;
 357                         clock-output-names = "apb0_spdif", "apb0_pio",
 358                                         "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
 359                                         "apb0_lradc", "apb0_gpadc", "apb0_twd",
 360                                         "apb0_cirtx";
 361                 };
 362
 363                 apb1_gates: clk@06000594 {
 364                         #clock-cells = <1>;
 365                         compatible = "allwinner,sun9i-a80-apb1-gates-clk";
 366                         reg = <0x06000594 0x4>;
 367                         clocks = <&apb1>;
 368                         clock-indices = <0>, <1>,
 369                                         <2>, <3>, <4>,
 370                                         <16>, <17>,
 371                                         <18>, <19>,
 372                                         <20>, <21>;
 373                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 374                                         "apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
 375                                         "apb1_uart0", "apb1_uart1",
 376                                         "apb1_uart2", "apb1_uart3",
 377                                         "apb1_uart4", "apb1_uart5";
 378                 };
 379
 380                 cpus_clk: clk@08001410 {
 381                         compatible = "allwinner,sun9i-a80-cpus-clk";
 382                         reg = <0x08001410 0x4>;
 383                         #clock-cells = <0>;
 384                         clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>;
 385                         clock-output-names = "cpus";
 386                 };
 387
 388                 ahbs: ahbs_clk {
 389                         compatible = "fixed-factor-clock";
 390                         #clock-cells = <0>;
 391                         clock-div = <1>;
 392                         clock-mult = <1>;
 393                         clocks = <&cpus_clk>;
 394                         clock-output-names = "ahbs";
 395                 };
 396
 397                 apbs: clk@0800141c {
 398                         compatible = "allwinner,sun8i-a23-apb0-clk";
 399                         reg = <0x0800141c 0x4>;
 400                         #clock-cells = <0>;
 401                         clocks = <&ahbs>;
 402                         clock-output-names = "apbs";
 403                 };
 404
 405                 apbs_gates: clk@08001428 {
 406                         compatible = "allwinner,sun9i-a80-apbs-gates-clk";
 407                         reg = <0x08001428 0x4>;
 408                         #clock-cells = <1>;
 409                         clocks = <&apbs>;
 410                         clock-indices = <0>, <1>,
 411                                         <2>, <3>,
 412                                         <4>, <5>,
 413                                         <6>, <7>,
 414                                         <12>, <13>,
 415                                         <16>, <17>,
 416                                         <18>, <20>;
 417                         clock-output-names = "apbs_pio", "apbs_ir",
 418                                         "apbs_timer", "apbs_rsb",
 419                                         "apbs_uart", "apbs_1wire",
 420                                         "apbs_i2c0", "apbs_i2c1",
 421                                         "apbs_ps2_0", "apbs_ps2_1",
 422                                         "apbs_dma", "apbs_i2s0",
 423                                         "apbs_i2s1", "apbs_twd";
 424                 };
 425
 426                 r_1wire_clk: clk@08001450 {
 427                         reg = <0x08001450 0x4>;
 428                         #clock-cells = <0>;
 429                         compatible = "allwinner,sun4i-a10-mod0-clk";
 430                         clocks = <&osc32k>, <&osc24M>;
 431                         clock-output-names = "r_1wire";
 432                 };
 433
 434                 r_ir_clk: clk@08001454 {
 435                         reg = <0x08001454 0x4>;
 436                         #clock-cells = <0>;
 437                         compatible = "allwinner,sun4i-a10-mod0-clk";
 438                         clocks = <&osc32k>, <&osc24M>;
 439                         clock-output-names = "r_ir";
 440                 };
 441         };
 442
 443         soc {
 444                 compatible = "simple-bus";
 445                 #address-cells = <1>;
 446                 #size-cells = <1>;
 447                 /*
 448                  * map 64 bit address range down to 32 bits,
 449                  * as the peripherals are all under 512MB.
 450                  */
 451                 ranges = <0 0 0 0x20000000>;
 452
 453                 ehci0: usb@00a00000 {
 454                         compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
 455                         reg = <0x00a00000 0x100>;
 456                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 457                         clocks = <&usb_mod_clk 1>;
 458                         resets = <&usb_mod_clk 17>;
 459                         phys = <&usbphy1>;
 460                         phy-names = "usb";
 461                         status = "disabled";
 462                 };
 463
 464                 ohci0: usb@00a00400 {
 465                         compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
 466                         reg = <0x00a00400 0x100>;
 467                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 468                         clocks = <&usb_mod_clk 1>, <&usb_mod_clk 2>;
 469                         resets = <&usb_mod_clk 17>;
 470                         phys = <&usbphy1>;
 471                         phy-names = "usb";
 472                         status = "disabled";
 473                 };
 474
 475                 usbphy1: phy@00a00800 {
 476                         compatible = "allwinner,sun9i-a80-usb-phy";
 477                         reg = <0x00a00800 0x4>;
 478                         clocks = <&usb_phy_clk 1>;
 479                         clock-names = "phy";
 480                         resets = <&usb_phy_clk 17>;
 481                         reset-names = "phy";
 482                         status = "disabled";
 483                         #phy-cells = <0>;
 484                 };
 485
 486                 ehci1: usb@00a01000 {
 487                         compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
 488                         reg = <0x00a01000 0x100>;
 489                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 490                         clocks = <&usb_mod_clk 3>;
 491                         resets = <&usb_mod_clk 18>;
 492                         phys = <&usbphy2>;
 493                         phy-names = "usb";
 494                         status = "disabled";
 495                 };
 496
 497                 usbphy2: phy@00a01800 {
 498                         compatible = "allwinner,sun9i-a80-usb-phy";
 499                         reg = <0x00a01800 0x4>;
 500                         clocks = <&usb_phy_clk 2>, <&usb_phy_clk 10>,
 501                                  <&usb_phy_clk 3>;
 502                         clock-names = "hsic_480M", "hsic_12M", "phy";
 503                         resets = <&usb_phy_clk 18>, <&usb_phy_clk 19>;
 504                         reset-names = "hsic", "phy";
 505                         status = "disabled";
 506                         #phy-cells = <0>;
 507                         /* usb1 is always used with HSIC */
 508                         phy_type = "hsic";
 509                 };
 510
 511                 ehci2: usb@00a02000 {
 512                         compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
 513                         reg = <0x00a02000 0x100>;
 514                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 515                         clocks = <&usb_mod_clk 5>;
 516                         resets = <&usb_mod_clk 19>;
 517                         phys = <&usbphy3>;
 518                         phy-names = "usb";
 519                         status = "disabled";
 520                 };
 521
 522                 ohci2: usb@00a02400 {
 523                         compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
 524                         reg = <0x00a02400 0x100>;
 525                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 526                         clocks = <&usb_mod_clk 5>, <&usb_mod_clk 6>;
 527                         resets = <&usb_mod_clk 19>;
 528                         phys = <&usbphy3>;
 529                         phy-names = "usb";
 530                         status = "disabled";
 531                 };
 532
 533                 usbphy3: phy@00a02800 {
 534                         compatible = "allwinner,sun9i-a80-usb-phy";
 535                         reg = <0x00a02800 0x4>;
 536                         clocks = <&usb_phy_clk 4>, <&usb_phy_clk 10>,
 537                                  <&usb_phy_clk 5>;
 538                         clock-names = "hsic_480M", "hsic_12M", "phy";
 539                         resets = <&usb_phy_clk 20>, <&usb_phy_clk 21>;
 540                         reset-names = "hsic", "phy";
 541                         status = "disabled";
 542                         #phy-cells = <0>;
 543                 };
 544
 545                 mmc0: mmc@01c0f000 {
 546                         compatible = "allwinner,sun9i-a80-mmc";
 547                         reg = <0x01c0f000 0x1000>;
 548                         clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>,
 549                                  <&mmc0_clk 1>, <&mmc0_clk 2>;
 550                         clock-names = "ahb", "mmc", "output", "sample";
 551                         resets = <&mmc_config_clk 0>;
 552                         reset-names = "ahb";
 553                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 554                         status = "disabled";
 555                         #address-cells = <1>;
 556                         #size-cells = <0>;
 557                 };
 558
 559                 mmc1: mmc@01c10000 {
 560                         compatible = "allwinner,sun9i-a80-mmc";
 561                         reg = <0x01c10000 0x1000>;
 562                         clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>,
 563                                  <&mmc1_clk 1>, <&mmc1_clk 2>;
 564                         clock-names = "ahb", "mmc", "output", "sample";
 565                         resets = <&mmc_config_clk 1>;
 566                         reset-names = "ahb";
 567                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 568                         status = "disabled";
 569                         #address-cells = <1>;
 570                         #size-cells = <0>;
 571                 };
 572
 573                 mmc2: mmc@01c11000 {
 574                         compatible = "allwinner,sun9i-a80-mmc";
 575                         reg = <0x01c11000 0x1000>;
 576                         clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>,
 577                                  <&mmc2_clk 1>, <&mmc2_clk 2>;
 578                         clock-names = "ahb", "mmc", "output", "sample";
 579                         resets = <&mmc_config_clk 2>;
 580                         reset-names = "ahb";
 581                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 582                         status = "disabled";
 583                         #address-cells = <1>;
 584                         #size-cells = <0>;
 585                 };
 586
 587                 mmc3: mmc@01c12000 {
 588                         compatible = "allwinner,sun9i-a80-mmc";
 589                         reg = <0x01c12000 0x1000>;
 590                         clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>,
 591                                  <&mmc3_clk 1>, <&mmc3_clk 2>;
 592                         clock-names = "ahb", "mmc", "output", "sample";
 593                         resets = <&mmc_config_clk 3>;
 594                         reset-names = "ahb";
 595                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 596                         status = "disabled";
 597                         #address-cells = <1>;
 598                         #size-cells = <0>;
 599                 };
 600
 601                 mmc_config_clk: clk@01c13000 {
 602                         compatible = "allwinner,sun9i-a80-mmc-config-clk";
 603                         reg = <0x01c13000 0x10>;
 604                         clocks = <&ahb0_gates 8>;
 605                         clock-names = "ahb";
 606                         resets = <&ahb0_resets 8>;
 607                         reset-names = "ahb";
 608                         #clock-cells = <1>;
 609                         #reset-cells = <1>;
 610                         clock-output-names = "mmc0_config", "mmc1_config",
 611                                              "mmc2_config", "mmc3_config";
 612                 };
 613
 614                 gic: interrupt-controller@01c41000 {
 615                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 616                         reg = <0x01c41000 0x1000>,
 617                               <0x01c42000 0x1000>,
 618                               <0x01c44000 0x2000>,
 619                               <0x01c46000 0x2000>;
 620                         interrupt-controller;
 621                         #interrupt-cells = <3>;
 622                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 623                 };
 624
 625                 ahb0_resets: reset@060005a0 {
 626                         #reset-cells = <1>;
 627                         compatible = "allwinner,sun6i-a31-clock-reset";
 628                         reg = <0x060005a0 0x4>;
 629                 };
 630
 631                 ahb1_resets: reset@060005a4 {
 632                         #reset-cells = <1>;
 633                         compatible = "allwinner,sun6i-a31-clock-reset";
 634                         reg = <0x060005a4 0x4>;
 635                 };
 636
 637                 ahb2_resets: reset@060005a8 {
 638                         #reset-cells = <1>;
 639                         compatible = "allwinner,sun6i-a31-clock-reset";
 640                         reg = <0x060005a8 0x4>;
 641                 };
 642
 643                 apb0_resets: reset@060005b0 {
 644                         #reset-cells = <1>;
 645                         compatible = "allwinner,sun6i-a31-clock-reset";
 646                         reg = <0x060005b0 0x4>;
 647                 };
 648
 649                 apb1_resets: reset@060005b4 {
 650                         #reset-cells = <1>;
 651                         compatible = "allwinner,sun6i-a31-clock-reset";
 652                         reg = <0x060005b4 0x4>;
 653                 };
 654
 655                 timer@06000c00 {
 656                         compatible = "allwinner,sun4i-a10-timer";
 657                         reg = <0x06000c00 0xa0>;
 658                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 659                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 660                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 661                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 662                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 663                                      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 664
 665                         clocks = <&osc24M>;
 666                 };
 667
 668                 wdt: watchdog@06000ca0 {
 669                         compatible = "allwinner,sun6i-a31-wdt";
 670                         reg = <0x06000ca0 0x20>;
 671                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 672                 };
 673
 674                 pio: pinctrl@06000800 {
 675                         compatible = "allwinner,sun9i-a80-pinctrl";
 676                         reg = <0x06000800 0x400>;
 677                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 678                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 679                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 680                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 681                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 682                         clocks = <&apb0_gates 5>;
 683                         gpio-controller;
 684                         interrupt-controller;
 685                         #interrupt-cells = <3>;
 686                         #size-cells = <0>;
 687                         #gpio-cells = <3>;
 688
 689                         i2c3_pins_a: i2c3@0 {
 690                                 allwinner,pins = "PG10", "PG11";
 691                                 allwinner,function = "i2c3";
 692                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 693                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 694                         };
 695
 696                         mmc0_pins: mmc0 {
 697                                 allwinner,pins = "PF0", "PF1" ,"PF2", "PF3",
 698                                                  "PF4", "PF5";
 699                                 allwinner,function = "mmc0";
 700                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 701                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 702                         };
 703
 704                         mmc1_pins: mmc1 {
 705                                 allwinner,pins = "PG0", "PG1" ,"PG2", "PG3",
 706                                                  "PG4", "PG5";
 707                                 allwinner,function = "mmc1";
 708                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 709                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 710                         };
 711
 712                         mmc2_8bit_pins: mmc2_8bit {
 713                                 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
 714                                                  "PC10", "PC11", "PC12",
 715                                                  "PC13", "PC14", "PC15",
 716                                                  "PC16";
 717                                 allwinner,function = "mmc2";
 718                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 719                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 720                         };
 721
 722                         uart0_pins_a: uart0@0 {
 723                                 allwinner,pins = "PH12", "PH13";
 724                                 allwinner,function = "uart0";
 725                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 726                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 727                         };
 728
 729                         uart4_pins_a: uart4@0 {
 730                                 allwinner,pins = "PG12", "PG13", "PG14", "PG15";
 731                                 allwinner,function = "uart4";
 732                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 733                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 734                         };
 735                 };
 736
 737                 uart0: serial@07000000 {
 738                         compatible = "snps,dw-apb-uart";
 739                         reg = <0x07000000 0x400>;
 740                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 741                         reg-shift = <2>;
 742                         reg-io-width = <4>;
 743                         clocks = <&apb1_gates 16>;
 744                         resets = <&apb1_resets 16>;
 745                         status = "disabled";
 746                 };
 747
 748                 uart1: serial@07000400 {
 749                         compatible = "snps,dw-apb-uart";
 750                         reg = <0x07000400 0x400>;
 751                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 752                         reg-shift = <2>;
 753                         reg-io-width = <4>;
 754                         clocks = <&apb1_gates 17>;
 755                         resets = <&apb1_resets 17>;
 756                         status = "disabled";
 757                 };
 758
 759                 uart2: serial@07000800 {
 760                         compatible = "snps,dw-apb-uart";
 761                         reg = <0x07000800 0x400>;
 762                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 763                         reg-shift = <2>;
 764                         reg-io-width = <4>;
 765                         clocks = <&apb1_gates 18>;
 766                         resets = <&apb1_resets 18>;
 767                         status = "disabled";
 768                 };
 769
 770                 uart3: serial@07000c00 {
 771                         compatible = "snps,dw-apb-uart";
 772                         reg = <0x07000c00 0x400>;
 773                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 774                         reg-shift = <2>;
 775                         reg-io-width = <4>;
 776                         clocks = <&apb1_gates 19>;
 777                         resets = <&apb1_resets 19>;
 778                         status = "disabled";
 779                 };
 780
 781                 uart4: serial@07001000 {
 782                         compatible = "snps,dw-apb-uart";
 783                         reg = <0x07001000 0x400>;
 784                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 785                         reg-shift = <2>;
 786                         reg-io-width = <4>;
 787                         clocks = <&apb1_gates 20>;
 788                         resets = <&apb1_resets 20>;
 789                         status = "disabled";
 790                 };
 791
 792                 uart5: serial@07001400 {
 793                         compatible = "snps,dw-apb-uart";
 794                         reg = <0x07001400 0x400>;
 795                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 796                         reg-shift = <2>;
 797                         reg-io-width = <4>;
 798                         clocks = <&apb1_gates 21>;
 799                         resets = <&apb1_resets 21>;
 800                         status = "disabled";
 801                 };
 802
 803                 i2c0: i2c@07002800 {
 804                         compatible = "allwinner,sun6i-a31-i2c";
 805                         reg = <0x07002800 0x400>;
 806                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 807                         clocks = <&apb1_gates 0>;
 808                         resets = <&apb1_resets 0>;
 809                         status = "disabled";
 810                         #address-cells = <1>;
 811                         #size-cells = <0>;
 812                 };
 813
 814                 i2c1: i2c@07002c00 {
 815                         compatible = "allwinner,sun6i-a31-i2c";
 816                         reg = <0x07002c00 0x400>;
 817                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 818                         clocks = <&apb1_gates 1>;
 819                         resets = <&apb1_resets 1>;
 820                         status = "disabled";
 821                         #address-cells = <1>;
 822                         #size-cells = <0>;
 823                 };
 824
 825                 i2c2: i2c@07003000 {
 826                         compatible = "allwinner,sun6i-a31-i2c";
 827                         reg = <0x07003000 0x400>;
 828                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 829                         clocks = <&apb1_gates 2>;
 830                         resets = <&apb1_resets 2>;
 831                         status = "disabled";
 832                         #address-cells = <1>;
 833                         #size-cells = <0>;
 834                 };
 835
 836                 i2c3: i2c@07003400 {
 837                         compatible = "allwinner,sun6i-a31-i2c";
 838                         reg = <0x07003400 0x400>;
 839                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 840                         clocks = <&apb1_gates 3>;
 841                         resets = <&apb1_resets 3>;
 842                         status = "disabled";
 843                         #address-cells = <1>;
 844                         #size-cells = <0>;
 845                 };
 846
 847                 i2c4: i2c@07003800 {
 848                         compatible = "allwinner,sun6i-a31-i2c";
 849                         reg = <0x07003800 0x400>;
 850                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 851                         clocks = <&apb1_gates 4>;
 852                         resets = <&apb1_resets 4>;
 853                         status = "disabled";
 854                         #address-cells = <1>;
 855                         #size-cells = <0>;
 856                 };
 857
 858                 r_wdt: watchdog@08001000 {
 859                         compatible = "allwinner,sun6i-a31-wdt";
 860                         reg = <0x08001000 0x20>;
 861                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 862                 };
 863
 864                 apbs_rst: reset@080014b0 {
 865                         reg = <0x080014b0 0x4>;
 866                         compatible = "allwinner,sun6i-a31-clock-reset";
 867                         #reset-cells = <1>;
 868                 };
 869
 870                 nmi_intc: interrupt-controller@080015a0 {
 871                         compatible = "allwinner,sun9i-a80-nmi";
 872                         interrupt-controller;
 873                         #interrupt-cells = <2>;
 874                         reg = <0x080015a0 0xc>;
 875                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 876                 };
 877
 878                 r_ir: ir@08002000 {
 879                         compatible = "allwinner,sun5i-a13-ir";
 880                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 881                         pinctrl-names = "default";
 882                         pinctrl-0 = <&r_ir_pins>;
 883                         clocks = <&apbs_gates 1>, <&r_ir_clk>;
 884                         clock-names = "apb", "ir";
 885                         resets = <&apbs_rst 1>;
 886                         reg = <0x08002000 0x40>;
 887                         status = "disabled";
 888                 };
 889
 890                 r_uart: serial@08002800 {
 891                         compatible = "snps,dw-apb-uart";
 892                         reg = <0x08002800 0x400>;
 893                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 894                         reg-shift = <2>;
 895                         reg-io-width = <4>;
 896                         clocks = <&apbs_gates 4>;
 897                         resets = <&apbs_rst 4>;
 898                         status = "disabled";
 899                 };
 900
 901                 r_pio: pinctrl@08002c00 {
 902                         compatible = "allwinner,sun9i-a80-r-pinctrl";
 903                         reg = <0x08002c00 0x400>;
 904                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 905                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 906                         clocks = <&apbs_gates 0>;
 907                         resets = <&apbs_rst 0>;
 908                         gpio-controller;
 909                         interrupt-controller;
 910                         #address-cells = <1>;
 911                         #size-cells = <0>;
 912                         #gpio-cells = <3>;
 913
 914                         r_ir_pins: r_ir {
 915                                 allwinner,pins = "PL6";
 916                                 allwinner,function = "s_cir_rx";
 917                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 918                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 919                         };
 920
 921                         r_rsb_pins: r_rsb {
 922                                 allwinner,pins = "PN0", "PN1";
 923                                 allwinner,function = "s_rsb";
 924                                 allwinner,drive = <SUN4I_PINCTRL_20_MA>;
 925                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 926                         };
 927                 };
 928
 929                 r_rsb: i2c@08003400 {
 930                         compatible = "allwinner,sun8i-a23-rsb";
 931                         reg = <0x08003400 0x400>;
 932                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 933                         clocks = <&apbs_gates 3>;
 934                         clock-frequency = <3000000>;
 935                         resets = <&apbs_rst 3>;
 936                         pinctrl-names = "default";
 937                         pinctrl-0 = <&r_rsb_pins>;
 938                         status = "disabled";
 939                         #address-cells = <1>;
 940                         #size-cells = <0>;
 941                 };
 942         };
 943 };