arch/arm/dts/sun8i-v3s.dtsi

   1 /*
   2  * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
  44 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/pinctrl/sun4i-a10.h>
  47
  48 / {
  49         #address-cells = <1>;
  50         #size-cells = <1>;
  51         interrupt-parent = <&gic>;
  52
  53         cpus {
  54                 #address-cells = <1>;
  55                 #size-cells = <0>;
  56
  57                 cpu@0 {
  58                         compatible = "arm,cortex-a7";
  59                         device_type = "cpu";
  60                         reg = <0>;
  61                         clocks = <&ccu CLK_CPU>;
  62                 };
  63         };
  64
  65         timer {
  66                 compatible = "arm,armv7-timer";
  67                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  68                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  69                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  70                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  71         };
  72
  73         clocks {
  74                 #address-cells = <1>;
  75                 #size-cells = <1>;
  76                 ranges;
  77
  78                 osc24M: osc24M_clk {
  79                         #clock-cells = <0>;
  80                         compatible = "fixed-clock";
  81                         clock-frequency = <24000000>;
  82                         clock-output-names = "osc24M";
  83                 };
  84
  85                 osc32k: osc32k_clk {
  86                         #clock-cells = <0>;
  87                         compatible = "fixed-clock";
  88                         clock-frequency = <32768>;
  89                         clock-output-names = "osc32k";
  90                 };
  91         };
  92
  93         soc {
  94                 compatible = "simple-bus";
  95                 #address-cells = <1>;
  96                 #size-cells = <1>;
  97                 ranges;
  98
  99                 mmc0: mmc@01c0f000 {
 100                         compatible = "allwinner,sun7i-a20-mmc";
 101                         reg = <0x01c0f000 0x1000>;
 102                         clocks = <&ccu CLK_BUS_MMC0>,
 103                                  <&ccu CLK_MMC0>,
 104                                  <&ccu CLK_MMC0_OUTPUT>,
 105                                  <&ccu CLK_MMC0_SAMPLE>;
 106                         clock-names = "ahb",
 107                                       "mmc",
 108                                       "output",
 109                                       "sample";
 110                         resets = <&ccu RST_BUS_MMC0>;
 111                         reset-names = "ahb";
 112                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 113                         status = "disabled";
 114                         #address-cells = <1>;
 115                         #size-cells = <0>;
 116                 };
 117
 118                 mmc1: mmc@01c10000 {
 119                         compatible = "allwinner,sun7i-a20-mmc";
 120                         reg = <0x01c10000 0x1000>;
 121                         clocks = <&ccu CLK_BUS_MMC1>,
 122                                  <&ccu CLK_MMC1>,
 123                                  <&ccu CLK_MMC1_OUTPUT>,
 124                                  <&ccu CLK_MMC1_SAMPLE>;
 125                         clock-names = "ahb",
 126                                       "mmc",
 127                                       "output",
 128                                       "sample";
 129                         resets = <&ccu RST_BUS_MMC1>;
 130                         reset-names = "ahb";
 131                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 132                         status = "disabled";
 133                         #address-cells = <1>;
 134                         #size-cells = <0>;
 135                 };
 136
 137                 mmc2: mmc@01c11000 {
 138                         compatible = "allwinner,sun7i-a20-mmc";
 139                         reg = <0x01c11000 0x1000>;
 140                         clocks = <&ccu CLK_BUS_MMC2>,
 141                                  <&ccu CLK_MMC2>,
 142                                  <&ccu CLK_MMC2_OUTPUT>,
 143                                  <&ccu CLK_MMC2_SAMPLE>;
 144                         clock-names = "ahb",
 145                                       "mmc",
 146                                       "output",
 147                                       "sample";
 148                         resets = <&ccu RST_BUS_MMC2>;
 149                         reset-names = "ahb";
 150                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 151                         status = "disabled";
 152                         #address-cells = <1>;
 153                         #size-cells = <0>;
 154                 };
 155
 156                 usb_otg: usb@01c19000 {
 157                         compatible = "allwinner,sun8i-h3-musb";
 158                         reg = <0x01c19000 0x0400>;
 159                         clocks = <&ccu CLK_BUS_OTG>;
 160                         resets = <&ccu RST_BUS_OTG>;
 161                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 162                         interrupt-names = "mc";
 163                         phys = <&usbphy 0>;
 164                         phy-names = "usb";
 165                         extcon = <&usbphy 0>;
 166                         status = "disabled";
 167                 };
 168
 169                 usbphy: phy@01c19400 {
 170                         compatible = "allwinner,sun8i-v3s-usb-phy";
 171                         reg = <0x01c19400 0x2c>,
 172                               <0x01c1a800 0x4>;
 173                         reg-names = "phy_ctrl",
 174                                     "pmu0";
 175                         clocks = <&ccu CLK_USB_PHY0>;
 176                         clock-names = "usb0_phy";
 177                         resets = <&ccu RST_USB_PHY0>;
 178                         reset-names = "usb0_reset";
 179                         status = "disabled";
 180                         #phy-cells = <1>;
 181                 };
 182
 183                 ccu: clock@01c20000 {
 184                         compatible = "allwinner,sun8i-v3s-ccu";
 185                         reg = <0x01c20000 0x400>;
 186                         clocks = <&osc24M>, <&osc32k>;
 187                         clock-names = "hosc", "losc";
 188                         #clock-cells = <1>;
 189                         #reset-cells = <1>;
 190                 };
 191
 192                 rtc: rtc@01c20400 {
 193                         compatible = "allwinner,sun6i-a31-rtc";
 194                         reg = <0x01c20400 0x54>;
 195                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 196                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 197                 };
 198
 199                 pio: pinctrl@01c20800 {
 200                         compatible = "allwinner,sun8i-v3s-pinctrl";
 201                         reg = <0x01c20800 0x400>;
 202                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 203                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 204                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
 205                         clock-names = "apb", "hosc", "losc";
 206                         gpio-controller;
 207                         #gpio-cells = <3>;
 208                         interrupt-controller;
 209                         #interrupt-cells = <3>;
 210
 211                         uart0_pins_a: uart0@0 {
 212                                 pins = "PB8", "PB9";
 213                                 function = "uart0";
 214                                 bias-pull-up;
 215                         };
 216
 217                         mmc0_pins_a: mmc0@0 {
 218                                 pins = "PF0", "PF1", "PF2", "PF3",
 219                                        "PF4", "PF5";
 220                                 function = "mmc0";
 221                                 drive-strength = <30>;
 222                                 bias-pull-up;
 223                         };
 224                 };
 225
 226                 timer@01c20c00 {
 227                         compatible = "allwinner,sun4i-a10-timer";
 228                         reg = <0x01c20c00 0xa0>;
 229                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 230                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 231                         clocks = <&osc24M>;
 232                 };
 233
 234                 wdt0: watchdog@01c20ca0 {
 235                         compatible = "allwinner,sun6i-a31-wdt";
 236                         reg = <0x01c20ca0 0x20>;
 237                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 238                 };
 239
 240                 uart0: serial@01c28000 {
 241                         compatible = "snps,dw-apb-uart";
 242                         reg = <0x01c28000 0x400>;
 243                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 244                         reg-shift = <2>;
 245                         reg-io-width = <4>;
 246                         clocks = <&ccu CLK_BUS_UART0>;
 247                         resets = <&ccu RST_BUS_UART0>;
 248                         status = "disabled";
 249                 };
 250
 251                 uart1: serial@01c28400 {
 252                         compatible = "snps,dw-apb-uart";
 253                         reg = <0x01c28400 0x400>;
 254                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 255                         reg-shift = <2>;
 256                         reg-io-width = <4>;
 257                         clocks = <&ccu CLK_BUS_UART1>;
 258                         resets = <&ccu RST_BUS_UART1>;
 259                         status = "disabled";
 260                 };
 261
 262                 uart2: serial@01c28800 {
 263                         compatible = "snps,dw-apb-uart";
 264                         reg = <0x01c28800 0x400>;
 265                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 266                         reg-shift = <2>;
 267                         reg-io-width = <4>;
 268                         clocks = <&ccu CLK_BUS_UART2>;
 269                         resets = <&ccu RST_BUS_UART2>;
 270                         status = "disabled";
 271                 };
 272
 273                 gic: interrupt-controller@01c81000 {
 274                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 275                         reg = <0x01c81000 0x1000>,
 276                               <0x01c82000 0x1000>,
 277                               <0x01c84000 0x2000>,
 278                               <0x01c86000 0x2000>;
 279                         interrupt-controller;
 280                         #interrupt-cells = <3>;
 281                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 282                 };
 283         };
 284 };