2 * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
3 * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/clock/sun8i-r40-ccu.h>
46 #include <dt-bindings/reset/sun8i-r40-ccu.h>
51 interrupt-parent = <&gic>;
60 compatible = "fixed-clock";
61 clock-frequency = <24000000>;
62 clock-output-names = "osc24M";
67 compatible = "fixed-clock";
68 clock-frequency = <32768>;
69 clock-output-names = "osc32k";
78 compatible = "arm,cortex-a7";
84 compatible = "arm,cortex-a7";
90 compatible = "arm,cortex-a7";
96 compatible = "arm,cortex-a7";
103 compatible = "simple-bus";
104 #address-cells = <1>;
108 nmi_intc: interrupt-controller@1c00030 {
109 compatible = "allwinner,sun7i-a20-sc-nmi";
110 interrupt-controller;
111 #interrupt-cells = <2>;
112 reg = <0x01c00030 0x0c>;
113 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
117 compatible = "allwinner,sun8i-r40-mmc",
118 "allwinner,sun50i-a64-mmc";
119 reg = <0x01c0f000 0x1000>;
120 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
121 clock-names = "ahb", "mmc";
122 resets = <&ccu RST_BUS_MMC0>;
124 pinctrl-0 = <&mmc0_pins>;
125 pinctrl-names = "default";
126 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
128 #address-cells = <1>;
133 compatible = "allwinner,sun8i-r40-mmc",
134 "allwinner,sun50i-a64-mmc";
135 reg = <0x01c10000 0x1000>;
136 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
137 clock-names = "ahb", "mmc";
138 resets = <&ccu RST_BUS_MMC1>;
140 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
142 #address-cells = <1>;
147 compatible = "allwinner,sun8i-r40-emmc",
148 "allwinner,sun50i-a64-emmc";
149 reg = <0x01c11000 0x1000>;
150 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
151 clock-names = "ahb", "mmc";
152 resets = <&ccu RST_BUS_MMC2>;
154 pinctrl-0 = <&mmc2_pins>;
155 pinctrl-names = "default";
156 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
158 #address-cells = <1>;
163 compatible = "allwinner,sun8i-r40-mmc",
164 "allwinner,sun50i-a64-mmc";
165 reg = <0x01c12000 0x1000>;
166 clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
167 clock-names = "ahb", "mmc";
168 resets = <&ccu RST_BUS_MMC3>;
170 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
172 #address-cells = <1>;
176 usbphy: phy@1c13400 {
177 compatible = "allwinner,sun8i-r40-usb-phy";
178 reg = <0x01c13400 0x14>,
182 reg-names = "phy_ctrl",
186 clocks = <&ccu CLK_USB_PHY0>,
189 clock-names = "usb0_phy",
192 resets = <&ccu RST_USB_PHY0>,
195 reset-names = "usb0_reset",
203 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
204 reg = <0x01c19000 0x100>;
205 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
206 clocks = <&ccu CLK_BUS_EHCI1>;
207 resets = <&ccu RST_BUS_EHCI1>;
214 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
215 reg = <0x01c19400 0x100>;
216 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&ccu CLK_BUS_OHCI1>,
218 <&ccu CLK_USB_OHCI1>;
219 resets = <&ccu RST_BUS_OHCI1>;
226 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
227 reg = <0x01c1c000 0x100>;
228 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&ccu CLK_BUS_EHCI2>;
230 resets = <&ccu RST_BUS_EHCI2>;
237 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
238 reg = <0x01c1c400 0x100>;
239 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&ccu CLK_BUS_OHCI2>,
241 <&ccu CLK_USB_OHCI2>;
242 resets = <&ccu RST_BUS_OHCI2>;
249 compatible = "allwinner,sun8i-r40-ccu";
250 reg = <0x01c20000 0x400>;
251 clocks = <&osc24M>, <&osc32k>;
252 clock-names = "hosc", "losc";
257 pio: pinctrl@1c20800 {
258 compatible = "allwinner,sun8i-r40-pinctrl";
259 reg = <0x01c20800 0x400>;
260 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
261 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
262 clock-names = "apb", "hosc", "losc";
264 interrupt-controller;
265 #interrupt-cells = <3>;
268 gmac_rgmii_pins: gmac-rgmii-pins {
269 pins = "PA0", "PA1", "PA2", "PA3",
270 "PA4", "PA5", "PA6", "PA7",
271 "PA8", "PA10", "PA11", "PA12",
272 "PA13", "PA15", "PA16";
275 * data lines in RGMII mode use DDR mode
276 * and need a higher signal drive strength
278 drive-strength = <40>;
281 i2c0_pins: i2c0-pins {
286 mmc0_pins: mmc0-pins {
287 pins = "PF0", "PF1", "PF2",
290 drive-strength = <30>;
294 mmc1_pg_pins: mmc1-pg-pins {
295 pins = "PG0", "PG1", "PG2",
298 drive-strength = <30>;
302 mmc2_pins: mmc2-pins {
303 pins = "PC5", "PC6", "PC7", "PC8", "PC9",
304 "PC10", "PC11", "PC12", "PC13", "PC14",
307 drive-strength = <30>;
311 uart0_pb_pins: uart0-pb-pins {
312 pins = "PB22", "PB23";
317 wdt: watchdog@1c20c90 {
318 compatible = "allwinner,sun4i-a10-wdt";
319 reg = <0x01c20c90 0x10>;
322 uart0: serial@1c28000 {
323 compatible = "snps,dw-apb-uart";
324 reg = <0x01c28000 0x400>;
325 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&ccu CLK_BUS_UART0>;
329 resets = <&ccu RST_BUS_UART0>;
333 uart1: serial@1c28400 {
334 compatible = "snps,dw-apb-uart";
335 reg = <0x01c28400 0x400>;
336 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&ccu CLK_BUS_UART1>;
340 resets = <&ccu RST_BUS_UART1>;
344 uart2: serial@1c28800 {
345 compatible = "snps,dw-apb-uart";
346 reg = <0x01c28800 0x400>;
347 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&ccu CLK_BUS_UART2>;
351 resets = <&ccu RST_BUS_UART2>;
355 uart3: serial@1c28c00 {
356 compatible = "snps,dw-apb-uart";
357 reg = <0x01c28c00 0x400>;
358 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&ccu CLK_BUS_UART3>;
362 resets = <&ccu RST_BUS_UART3>;
366 uart4: serial@1c29000 {
367 compatible = "snps,dw-apb-uart";
368 reg = <0x01c29000 0x400>;
369 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&ccu CLK_BUS_UART4>;
373 resets = <&ccu RST_BUS_UART4>;
377 uart5: serial@1c29400 {
378 compatible = "snps,dw-apb-uart";
379 reg = <0x01c29400 0x400>;
380 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&ccu CLK_BUS_UART5>;
384 resets = <&ccu RST_BUS_UART5>;
388 uart6: serial@1c29800 {
389 compatible = "snps,dw-apb-uart";
390 reg = <0x01c29800 0x400>;
391 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&ccu CLK_BUS_UART6>;
395 resets = <&ccu RST_BUS_UART6>;
399 uart7: serial@1c29c00 {
400 compatible = "snps,dw-apb-uart";
401 reg = <0x01c29c00 0x400>;
402 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&ccu CLK_BUS_UART7>;
406 resets = <&ccu RST_BUS_UART7>;
411 compatible = "allwinner,sun6i-a31-i2c";
412 reg = <0x01c2ac00 0x400>;
413 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&ccu CLK_BUS_I2C0>;
415 resets = <&ccu RST_BUS_I2C0>;
416 pinctrl-0 = <&i2c0_pins>;
417 pinctrl-names = "default";
419 #address-cells = <1>;
424 compatible = "allwinner,sun6i-a31-i2c";
425 reg = <0x01c2b000 0x400>;
426 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&ccu CLK_BUS_I2C1>;
428 resets = <&ccu RST_BUS_I2C1>;
430 #address-cells = <1>;
435 compatible = "allwinner,sun6i-a31-i2c";
436 reg = <0x01c2b400 0x400>;
437 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&ccu CLK_BUS_I2C2>;
439 resets = <&ccu RST_BUS_I2C2>;
441 #address-cells = <1>;
446 compatible = "allwinner,sun6i-a31-i2c";
447 reg = <0x01c2b800 0x400>;
448 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&ccu CLK_BUS_I2C3>;
450 resets = <&ccu RST_BUS_I2C3>;
452 #address-cells = <1>;
457 compatible = "allwinner,sun6i-a31-i2c";
458 reg = <0x01c2c000 0x400>;
459 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&ccu CLK_BUS_I2C4>;
461 resets = <&ccu RST_BUS_I2C4>;
463 #address-cells = <1>;
467 gmac: ethernet@1c50000 {
468 compatible = "allwinner,sun8i-r40-gmac";
470 reg = <0x01c50000 0x10000>;
471 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
472 interrupt-names = "macirq";
473 resets = <&ccu RST_BUS_GMAC>;
474 reset-names = "stmmaceth";
475 clocks = <&ccu CLK_BUS_GMAC>;
476 clock-names = "stmmaceth";
477 #address-cells = <1>;
482 compatible = "snps,dwmac-mdio";
483 #address-cells = <1>;
488 gic: interrupt-controller@1c81000 {
489 compatible = "arm,gic-400";
490 reg = <0x01c81000 0x1000>,
494 interrupt-controller;
495 #interrupt-cells = <3>;
496 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
501 compatible = "arm,armv7-timer";
502 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
503 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
504 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
505 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;