arch/arm/dts/sun8i-h3.dtsi

   1 /*
   2  * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include "skeleton.dtsi"
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/pinctrl/sun4i-a10.h>
  47
  48 / {
  49         interrupt-parent = <&gic>;
  50
  51         aliases {
  52                 ethernet0 = <&emac>;
  53         };
  54
  55         cpus {
  56                 #address-cells = <1>;
  57                 #size-cells = <0>;
  58
  59                 cpu@0 {
  60                         compatible = "arm,cortex-a7";
  61                         device_type = "cpu";
  62                         reg = <0>;
  63                 };
  64
  65                 cpu@1 {
  66                         compatible = "arm,cortex-a7";
  67                         device_type = "cpu";
  68                         reg = <1>;
  69                 };
  70
  71                 cpu@2 {
  72                         compatible = "arm,cortex-a7";
  73                         device_type = "cpu";
  74                         reg = <2>;
  75                 };
  76
  77                 cpu@3 {
  78                         compatible = "arm,cortex-a7";
  79                         device_type = "cpu";
  80                         reg = <3>;
  81                 };
  82         };
  83
  84         timer {
  85                 compatible = "arm,armv7-timer";
  86                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  87                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  88                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  89                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  90         };
  91
  92         clocks {
  93                 #address-cells = <1>;
  94                 #size-cells = <1>;
  95                 ranges;
  96
  97                 osc24M: osc24M_clk {
  98                         #clock-cells = <0>;
  99                         compatible = "fixed-clock";
 100                         clock-frequency = <24000000>;
 101                         clock-output-names = "osc24M";
 102                 };
 103
 104                 osc32k: osc32k_clk {
 105                         #clock-cells = <0>;
 106                         compatible = "fixed-clock";
 107                         clock-frequency = <32768>;
 108                         clock-output-names = "osc32k";
 109                 };
 110
 111                 pll1: clk@01c20000 {
 112                         #clock-cells = <0>;
 113                         compatible = "allwinner,sun8i-a23-pll1-clk";
 114                         reg = <0x01c20000 0x4>;
 115                         clocks = <&osc24M>;
 116                         clock-output-names = "pll1";
 117                 };
 118
 119                 /* dummy clock until actually implemented */
 120                 pll5: pll5_clk {
 121                         #clock-cells = <0>;
 122                         compatible = "fixed-clock";
 123                         clock-frequency = <0>;
 124                         clock-output-names = "pll5";
 125                 };
 126
 127                 pll6: clk@01c20028 {
 128                         #clock-cells = <1>;
 129                         compatible = "allwinner,sun6i-a31-pll6-clk";
 130                         reg = <0x01c20028 0x4>;
 131                         clocks = <&osc24M>;
 132                         clock-output-names = "pll6", "pll6x2";
 133                 };
 134
 135                 pll6d2: pll6d2_clk {
 136                         #clock-cells = <0>;
 137                         compatible = "fixed-factor-clock";
 138                         clock-div = <2>;
 139                         clock-mult = <1>;
 140                         clocks = <&pll6 0>;
 141                         clock-output-names = "pll6d2";
 142                 };
 143
 144                 /* dummy clock until pll6 can be reused */
 145                 pll8: pll8_clk {
 146                         #clock-cells = <0>;
 147                         compatible = "fixed-clock";
 148                         clock-frequency = <1>;
 149                         clock-output-names = "pll8";
 150                 };
 151
 152                 cpu: cpu_clk@01c20050 {
 153                         #clock-cells = <0>;
 154                         compatible = "allwinner,sun4i-a10-cpu-clk";
 155                         reg = <0x01c20050 0x4>;
 156                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
 157                         clock-output-names = "cpu";
 158                 };
 159
 160                 axi: axi_clk@01c20050 {
 161                         #clock-cells = <0>;
 162                         compatible = "allwinner,sun4i-a10-axi-clk";
 163                         reg = <0x01c20050 0x4>;
 164                         clocks = <&cpu>;
 165                         clock-output-names = "axi";
 166                 };
 167
 168                 ahb1: ahb1_clk@01c20054 {
 169                         #clock-cells = <0>;
 170                         compatible = "allwinner,sun6i-a31-ahb1-clk";
 171                         reg = <0x01c20054 0x4>;
 172                         clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
 173                         clock-output-names = "ahb1";
 174                 };
 175
 176                 ahb2: ahb2_clk@01c2005c {
 177                         #clock-cells = <0>;
 178                         compatible = "allwinner,sun8i-h3-ahb2-clk";
 179                         reg = <0x01c2005c 0x4>;
 180                         clocks = <&ahb1>, <&pll6d2>;
 181                         clock-output-names = "ahb2";
 182                 };
 183
 184                 apb1: apb1_clk@01c20054 {
 185                         #clock-cells = <0>;
 186                         compatible = "allwinner,sun4i-a10-apb0-clk";
 187                         reg = <0x01c20054 0x4>;
 188                         clocks = <&ahb1>;
 189                         clock-output-names = "apb1";
 190                 };
 191
 192                 apb2: apb2_clk@01c20058 {
 193                         #clock-cells = <0>;
 194                         compatible = "allwinner,sun4i-a10-apb1-clk";
 195                         reg = <0x01c20058 0x4>;
 196                         clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
 197                         clock-output-names = "apb2";
 198                 };
 199
 200                 bus_gates: clk@01c20060 {
 201                         #clock-cells = <1>;
 202                         compatible = "allwinner,sun8i-h3-bus-gates-clk";
 203                         reg = <0x01c20060 0x14>;
 204                         clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
 205                         clock-names = "ahb1", "ahb2", "apb1", "apb2";
 206                         clock-indices = <5>, <6>, <8>,
 207                                         <9>, <10>, <13>,
 208                                         <14>, <17>, <18>,
 209                                         <19>, <20>,
 210                                         <21>, <23>,
 211                                         <24>, <25>,
 212                                         <26>, <27>,
 213                                         <28>, <29>,
 214                                         <30>, <31>, <32>,
 215                                         <35>, <36>, <37>,
 216                                         <40>, <41>, <43>,
 217                                         <44>, <52>, <53>,
 218                                         <54>, <64>,
 219                                         <65>, <69>, <72>,
 220                                         <76>, <77>, <78>,
 221                                         <96>, <97>, <98>,
 222                                         <112>, <113>,
 223                                         <114>, <115>,
 224                                         <116>, <128>, <135>;
 225                         clock-output-names = "bus_ce", "bus_dma", "bus_mmc0",
 226                                              "bus_mmc1", "bus_mmc2", "bus_nand",
 227                                              "bus_sdram", "bus_gmac", "bus_ts",
 228                                              "bus_hstimer", "bus_spi0",
 229                                              "bus_spi1", "bus_otg",
 230                                              "bus_otg_ehci0", "bus_ehci1",
 231                                              "bus_ehci2", "bus_ehci3",
 232                                              "bus_otg_ohci0", "bus_ohci1",
 233                                              "bus_ohci2", "bus_ohci3", "bus_ve",
 234                                              "bus_lcd0", "bus_lcd1", "bus_deint",
 235                                              "bus_csi", "bus_tve", "bus_hdmi",
 236                                              "bus_de", "bus_gpu", "bus_msgbox",
 237                                              "bus_spinlock", "bus_codec",
 238                                              "bus_spdif", "bus_pio", "bus_ths",
 239                                              "bus_i2s0", "bus_i2s1", "bus_i2s2",
 240                                              "bus_i2c0", "bus_i2c1", "bus_i2c2",
 241                                              "bus_uart0", "bus_uart1",
 242                                              "bus_uart2", "bus_uart3",
 243                                              "bus_scr", "bus_ephy", "bus_dbg";
 244                 };
 245
 246                 mmc0_clk: clk@01c20088 {
 247                         #clock-cells = <1>;
 248                         compatible = "allwinner,sun4i-a10-mmc-clk";
 249                         reg = <0x01c20088 0x4>;
 250                         clocks = <&osc24M>, <&pll6 0>, <&pll8>;
 251                         clock-output-names = "mmc0",
 252                                              "mmc0_output",
 253                                              "mmc0_sample";
 254                 };
 255
 256                 mmc1_clk: clk@01c2008c {
 257                         #clock-cells = <1>;
 258                         compatible = "allwinner,sun4i-a10-mmc-clk";
 259                         reg = <0x01c2008c 0x4>;
 260                         clocks = <&osc24M>, <&pll6 0>, <&pll8>;
 261                         clock-output-names = "mmc1",
 262                                              "mmc1_output",
 263                                              "mmc1_sample";
 264                 };
 265
 266                 mmc2_clk: clk@01c20090 {
 267                         #clock-cells = <1>;
 268                         compatible = "allwinner,sun4i-a10-mmc-clk";
 269                         reg = <0x01c20090 0x4>;
 270                         clocks = <&osc24M>, <&pll6 0>, <&pll8>;
 271                         clock-output-names = "mmc2",
 272                                              "mmc2_output",
 273                                              "mmc2_sample";
 274                 };
 275
 276                 usb_clk: clk@01c200cc {
 277                         #clock-cells = <1>;
 278                         #reset-cells = <1>;
 279                         compatible = "allwinner,sun8i-h3-usb-clk";
 280                         reg = <0x01c200cc 0x4>;
 281                         clocks = <&osc24M>;
 282                         clock-output-names = "usb_phy0", "usb_phy1",
 283                                              "usb_phy2", "usb_phy3",
 284                                              "usb_ohci0", "usb_ohci1",
 285                                              "usb_ohci2", "usb_ohci3";
 286                 };
 287
 288                 mbus_clk: clk@01c2015c {
 289                         #clock-cells = <0>;
 290                         compatible = "allwinner,sun8i-a23-mbus-clk";
 291                         reg = <0x01c2015c 0x4>;
 292                         clocks = <&osc24M>, <&pll6 1>, <&pll5>;
 293                         clock-output-names = "mbus";
 294                 };
 295
 296                 apb0: apb0_clk {
 297                         compatible = "fixed-factor-clock";
 298                         #clock-cells = <0>;
 299                         clock-div = <1>;
 300                         clock-mult = <1>;
 301                         clocks = <&osc24M>;
 302                         clock-output-names = "apb0";
 303                 };
 304
 305                 apb0_gates: clk@01f01428 {
 306                         compatible = "allwinner,sun8i-h3-apb0-gates-clk",
 307                                      "allwinner,sun4i-a10-gates-clk";
 308                         reg = <0x01f01428 0x4>;
 309                         #clock-cells = <1>;
 310                         clocks = <&apb0>;
 311                         clock-indices = <0>, <1>;
 312                         clock-output-names = "apb0_pio", "apb0_ir";
 313                 };
 314
 315                 ir_clk: ir_clk@01f01454 {
 316                         compatible = "allwinner,sun4i-a10-mod0-clk";
 317                         reg = <0x01f01454 0x4>;
 318                         #clock-cells = <0>;
 319                         clocks = <&osc32k>, <&osc24M>;
 320                         clock-output-names = "ir";
 321                 };
 322         };
 323
 324         soc {
 325                 compatible = "simple-bus";
 326                 #address-cells = <1>;
 327                 #size-cells = <1>;
 328                 ranges;
 329
 330                 dma: dma-controller@01c02000 {
 331                         compatible = "allwinner,sun8i-h3-dma";
 332                         reg = <0x01c02000 0x1000>;
 333                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 334                         clocks = <&bus_gates 6>;
 335                         resets = <&ahb_rst 6>;
 336                         #dma-cells = <1>;
 337                 };
 338
 339                 mmc0: mmc@01c0f000 {
 340                         compatible = "allwinner,sun5i-a13-mmc";
 341                         reg = <0x01c0f000 0x1000>;
 342                         clocks = <&bus_gates 8>,
 343                                  <&mmc0_clk 0>,
 344                                  <&mmc0_clk 1>,
 345                                  <&mmc0_clk 2>;
 346                         clock-names = "ahb",
 347                                       "mmc",
 348                                       "output",
 349                                       "sample";
 350                         resets = <&ahb_rst 8>;
 351                         reset-names = "ahb";
 352                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 353                         status = "disabled";
 354                         #address-cells = <1>;
 355                         #size-cells = <0>;
 356                 };
 357
 358                 mmc1: mmc@01c10000 {
 359                         compatible = "allwinner,sun5i-a13-mmc";
 360                         reg = <0x01c10000 0x1000>;
 361                         clocks = <&bus_gates 9>,
 362                                  <&mmc1_clk 0>,
 363                                  <&mmc1_clk 1>,
 364                                  <&mmc1_clk 2>;
 365                         clock-names = "ahb",
 366                                       "mmc",
 367                                       "output",
 368                                       "sample";
 369                         resets = <&ahb_rst 9>;
 370                         reset-names = "ahb";
 371                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 372                         status = "disabled";
 373                         #address-cells = <1>;
 374                         #size-cells = <0>;
 375                 };
 376
 377                 mmc2: mmc@01c11000 {
 378                         compatible = "allwinner,sun5i-a13-mmc";
 379                         reg = <0x01c11000 0x1000>;
 380                         clocks = <&bus_gates 10>,
 381                                  <&mmc2_clk 0>,
 382                                  <&mmc2_clk 1>,
 383                                  <&mmc2_clk 2>;
 384                         clock-names = "ahb",
 385                                       "mmc",
 386                                       "output",
 387                                       "sample";
 388                         resets = <&ahb_rst 10>;
 389                         reset-names = "ahb";
 390                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 391                         status = "disabled";
 392                         #address-cells = <1>;
 393                         #size-cells = <0>;
 394                 };
 395
 396                 usbphy: phy@01c19400 {
 397                         compatible = "allwinner,sun8i-h3-usb-phy";
 398                         reg = <0x01c19400 0x2c>,
 399                               <0x01c1a800 0x4>,
 400                               <0x01c1b800 0x4>,
 401                               <0x01c1c800 0x4>,
 402                               <0x01c1d800 0x4>;
 403                         reg-names = "phy_ctrl",
 404                                     "pmu0",
 405                                     "pmu1",
 406                                     "pmu2",
 407                                     "pmu3";
 408                         clocks = <&usb_clk 8>,
 409                                  <&usb_clk 9>,
 410                                  <&usb_clk 10>,
 411                                  <&usb_clk 11>;
 412                         clock-names = "usb0_phy",
 413                                       "usb1_phy",
 414                                       "usb2_phy",
 415                                       "usb3_phy";
 416                         resets = <&usb_clk 0>,
 417                                  <&usb_clk 1>,
 418                                  <&usb_clk 2>,
 419                                  <&usb_clk 3>;
 420                         reset-names = "usb0_reset",
 421                                       "usb1_reset",
 422                                       "usb2_reset",
 423                                       "usb3_reset";
 424                         status = "disabled";
 425                         #phy-cells = <1>;
 426                 };
 427
 428                 ehci1: usb@01c1b000 {
 429                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 430                         reg = <0x01c1b000 0x100>;
 431                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 432                         clocks = <&bus_gates 25>, <&bus_gates 29>;
 433                         resets = <&ahb_rst 25>, <&ahb_rst 29>;
 434                         phys = <&usbphy 1>;
 435                         phy-names = "usb";
 436                         status = "disabled";
 437                 };
 438
 439                 ohci1: usb@01c1b400 {
 440                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 441                         reg = <0x01c1b400 0x100>;
 442                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 443                         clocks = <&bus_gates 29>, <&bus_gates 25>,
 444                                  <&usb_clk 17>;
 445                         resets = <&ahb_rst 29>, <&ahb_rst 25>;
 446                         phys = <&usbphy 1>;
 447                         phy-names = "usb";
 448                         status = "disabled";
 449                 };
 450
 451                 ehci2: usb@01c1c000 {
 452                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 453                         reg = <0x01c1c000 0x100>;
 454                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 455                         clocks = <&bus_gates 26>, <&bus_gates 30>;
 456                         resets = <&ahb_rst 26>, <&ahb_rst 30>;
 457                         phys = <&usbphy 2>;
 458                         phy-names = "usb";
 459                         status = "disabled";
 460                 };
 461
 462                 ohci2: usb@01c1c400 {
 463                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 464                         reg = <0x01c1c400 0x100>;
 465                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 466                         clocks = <&bus_gates 30>, <&bus_gates 26>,
 467                                  <&usb_clk 18>;
 468                         resets = <&ahb_rst 30>, <&ahb_rst 26>;
 469                         phys = <&usbphy 2>;
 470                         phy-names = "usb";
 471                         status = "disabled";
 472                 };
 473
 474                 ehci3: usb@01c1d000 {
 475                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 476                         reg = <0x01c1d000 0x100>;
 477                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 478                         clocks = <&bus_gates 27>, <&bus_gates 31>;
 479                         resets = <&ahb_rst 27>, <&ahb_rst 31>;
 480                         phys = <&usbphy 3>;
 481                         phy-names = "usb";
 482                         status = "disabled";
 483                 };
 484
 485                 ohci3: usb@01c1d400 {
 486                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 487                         reg = <0x01c1d400 0x100>;
 488                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 489                         clocks = <&bus_gates 31>, <&bus_gates 27>,
 490                                  <&usb_clk 19>;
 491                         resets = <&ahb_rst 31>, <&ahb_rst 27>;
 492                         phys = <&usbphy 3>;
 493                         phy-names = "usb";
 494                         status = "disabled";
 495                 };
 496
 497                 pio: pinctrl@01c20800 {
 498                         compatible = "allwinner,sun8i-h3-pinctrl";
 499                         reg = <0x01c20800 0x400>;
 500                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 501                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 502                         clocks = <&bus_gates 69>;
 503                         gpio-controller;
 504                         #gpio-cells = <3>;
 505                         interrupt-controller;
 506                         #interrupt-cells = <3>;
 507
 508                         rgmii_pins: rgmii_pins {
 509                                 allwinner,pins = "PD0", "PD1", "PD2", "PD3",
 510                                                  "PD4", "PD5", "PD7",
 511                                                  "PD8", "PD9", "PD10",
 512                                                  "PD12", "PD13", "PD15",
 513                                                  "PD16", "PD17";
 514                                 allwinner,function = "emac";
 515                                 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
 516                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 517                         };
 518
 519                         uart0_pins_a: uart0@0 {
 520                                 allwinner,pins = "PA4", "PA5";
 521                                 allwinner,function = "uart0";
 522                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 523                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 524                         };
 525
 526                         mmc0_pins_a: mmc0@0 {
 527                                 allwinner,pins = "PF0", "PF1", "PF2", "PF3",
 528                                                  "PF4", "PF5";
 529                                 allwinner,function = "mmc0";
 530                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 531                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 532                         };
 533
 534                         mmc0_cd_pin: mmc0_cd_pin@0 {
 535                                 allwinner,pins = "PF6";
 536                                 allwinner,function = "gpio_in";
 537                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 538                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 539                         };
 540
 541                         mmc1_pins_a: mmc1@0 {
 542                                 allwinner,pins = "PG0", "PG1", "PG2", "PG3",
 543                                                  "PG4", "PG5";
 544                                 allwinner,function = "mmc1";
 545                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 546                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 547                         };
 548
 549                         mmc2_8bit_pins: mmc2_8bit {
 550                                 allwinner,pins = "PC5", "PC6", "PC8",
 551                                                  "PC9", "PC10", "PC11",
 552                                                  "PC12", "PC13", "PC14",
 553                                                  "PC15", "PC16";
 554                                 allwinner,function = "mmc2";
 555                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 556                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 557                         };
 558                 };
 559
 560                 ahb_rst: reset@01c202c0 {
 561                         #reset-cells = <1>;
 562                         compatible = "allwinner,sun6i-a31-ahb1-reset";
 563                         reg = <0x01c202c0 0xc>;
 564                 };
 565
 566                 apb1_rst: reset@01c202d0 {
 567                         #reset-cells = <1>;
 568                         compatible = "allwinner,sun6i-a31-clock-reset";
 569                         reg = <0x01c202d0 0x4>;
 570                 };
 571
 572                 apb2_rst: reset@01c202d8 {
 573                         #reset-cells = <1>;
 574                         compatible = "allwinner,sun6i-a31-clock-reset";
 575                         reg = <0x01c202d8 0x4>;
 576                 };
 577
 578                 timer@01c20c00 {
 579                         compatible = "allwinner,sun4i-a10-timer";
 580                         reg = <0x01c20c00 0xa0>;
 581                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 582                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 583                         clocks = <&osc24M>;
 584                 };
 585
 586                 wdt0: watchdog@01c20ca0 {
 587                         compatible = "allwinner,sun6i-a31-wdt";
 588                         reg = <0x01c20ca0 0x20>;
 589                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 590                 };
 591
 592                 uart0: serial@01c28000 {
 593                         compatible = "snps,dw-apb-uart";
 594                         reg = <0x01c28000 0x400>;
 595                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 596                         reg-shift = <2>;
 597                         reg-io-width = <4>;
 598                         clocks = <&bus_gates 112>;
 599                         resets = <&apb2_rst 16>;
 600                         dmas = <&dma 6>, <&dma 6>;
 601                         dma-names = "rx", "tx";
 602                         status = "disabled";
 603                 };
 604
 605                 uart1: serial@01c28400 {
 606                         compatible = "snps,dw-apb-uart";
 607                         reg = <0x01c28400 0x400>;
 608                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 609                         reg-shift = <2>;
 610                         reg-io-width = <4>;
 611                         clocks = <&bus_gates 113>;
 612                         resets = <&apb2_rst 17>;
 613                         dmas = <&dma 7>, <&dma 7>;
 614                         dma-names = "rx", "tx";
 615                         status = "disabled";
 616                 };
 617
 618                 uart2: serial@01c28800 {
 619                         compatible = "snps,dw-apb-uart";
 620                         reg = <0x01c28800 0x400>;
 621                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 622                         reg-shift = <2>;
 623                         reg-io-width = <4>;
 624                         clocks = <&bus_gates 114>;
 625                         resets = <&apb2_rst 18>;
 626                         dmas = <&dma 8>, <&dma 8>;
 627                         dma-names = "rx", "tx";
 628                         status = "disabled";
 629                 };
 630
 631                 uart3: serial@01c28c00 {
 632                         compatible = "snps,dw-apb-uart";
 633                         reg = <0x01c28c00 0x400>;
 634                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 635                         reg-shift = <2>;
 636                         reg-io-width = <4>;
 637                         clocks = <&bus_gates 115>;
 638                         resets = <&apb2_rst 19>;
 639                         dmas = <&dma 9>, <&dma 9>;
 640                         dma-names = "rx", "tx";
 641                         status = "disabled";
 642                 };
 643
 644                 emac: ethernet@01c30000 {
 645                         compatible = "allwinner,sun8i-h3-emac";
 646                         reg = <0x01c30000 0x2000>, <0x01c00030 0x4>;
 647                         reg-names = "emac", "syscon";
 648                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 649                         resets = <&ahb_rst 17>, <&ahb_rst 66>;
 650                         reset-names = "ahb", "ephy";
 651                         clocks = <&bus_gates 17>, <&bus_gates 128>;
 652                         clock-names = "ahb", "ephy";
 653                         #address-cells = <1>;
 654                         #size-cells = <0>;
 655                         status = "disabled";
 656                 };
 657
 658                 gic: interrupt-controller@01c81000 {
 659                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 660                         reg = <0x01c81000 0x1000>,
 661                               <0x01c82000 0x1000>,
 662                               <0x01c84000 0x2000>,
 663                               <0x01c86000 0x2000>;
 664                         interrupt-controller;
 665                         #interrupt-cells = <3>;
 666                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 667                 };
 668
 669                 rtc: rtc@01f00000 {
 670                         compatible = "allwinner,sun6i-a31-rtc";
 671                         reg = <0x01f00000 0x54>;
 672                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 673                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 674                 };
 675
 676                 apb0_reset: reset@01f014b0 {
 677                         reg = <0x01f014b0 0x4>;
 678                         compatible = "allwinner,sun6i-a31-clock-reset";
 679                         #reset-cells = <1>;
 680                 };
 681
 682                 ir: ir@01f02000 {
 683                         compatible = "allwinner,sun5i-a13-ir";
 684                         clocks = <&apb0_gates 1>, <&ir_clk>;
 685                         clock-names = "apb", "ir";
 686                         resets = <&apb0_reset 1>;
 687                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 688                         reg = <0x01f02000 0x40>;
 689                         status = "disabled";
 690                 };
 691
 692                 r_pio: pinctrl@01f02c00 {
 693                         compatible = "allwinner,sun8i-h3-r-pinctrl";
 694                         reg = <0x01f02c00 0x400>;
 695                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 696                         clocks = <&apb0_gates 0>;
 697                         resets = <&apb0_reset 0>;
 698                         gpio-controller;
 699                         #gpio-cells = <3>;
 700                         interrupt-controller;
 701                         #interrupt-cells = <3>;
 702
 703                         ir_pins_a: ir@0 {
 704                                 allwinner,pins = "PL11";
 705                                 allwinner,function = "s_cir_rx";
 706                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 707                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 708                         };
 709                 };
 710         };
 711 };