2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include "skeleton.dtsi"
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/pinctrl/sun4i-a10.h>
49 interrupt-parent = <&gic>;
60 compatible = "arm,cortex-a7";
66 compatible = "arm,cortex-a7";
72 compatible = "arm,cortex-a7";
78 compatible = "arm,cortex-a7";
85 compatible = "arm,armv7-timer";
86 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
87 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
88 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
89 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
99 compatible = "fixed-clock";
100 clock-frequency = <24000000>;
101 clock-output-names = "osc24M";
106 compatible = "fixed-clock";
107 clock-frequency = <32768>;
108 clock-output-names = "osc32k";
113 compatible = "allwinner,sun8i-a23-pll1-clk";
114 reg = <0x01c20000 0x4>;
116 clock-output-names = "pll1";
119 /* dummy clock until actually implemented */
122 compatible = "fixed-clock";
123 clock-frequency = <0>;
124 clock-output-names = "pll5";
129 compatible = "allwinner,sun6i-a31-pll6-clk";
130 reg = <0x01c20028 0x4>;
132 clock-output-names = "pll6", "pll6x2";
137 compatible = "fixed-factor-clock";
141 clock-output-names = "pll6d2";
144 /* dummy clock until pll6 can be reused */
147 compatible = "fixed-clock";
148 clock-frequency = <1>;
149 clock-output-names = "pll8";
152 cpu: cpu_clk@01c20050 {
154 compatible = "allwinner,sun4i-a10-cpu-clk";
155 reg = <0x01c20050 0x4>;
156 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
157 clock-output-names = "cpu";
160 axi: axi_clk@01c20050 {
162 compatible = "allwinner,sun4i-a10-axi-clk";
163 reg = <0x01c20050 0x4>;
165 clock-output-names = "axi";
168 ahb1: ahb1_clk@01c20054 {
170 compatible = "allwinner,sun6i-a31-ahb1-clk";
171 reg = <0x01c20054 0x4>;
172 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
173 clock-output-names = "ahb1";
176 ahb2: ahb2_clk@01c2005c {
178 compatible = "allwinner,sun8i-h3-ahb2-clk";
179 reg = <0x01c2005c 0x4>;
180 clocks = <&ahb1>, <&pll6d2>;
181 clock-output-names = "ahb2";
184 apb1: apb1_clk@01c20054 {
186 compatible = "allwinner,sun4i-a10-apb0-clk";
187 reg = <0x01c20054 0x4>;
189 clock-output-names = "apb1";
192 apb2: apb2_clk@01c20058 {
194 compatible = "allwinner,sun4i-a10-apb1-clk";
195 reg = <0x01c20058 0x4>;
196 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
197 clock-output-names = "apb2";
200 bus_gates: clk@01c20060 {
202 compatible = "allwinner,sun8i-h3-bus-gates-clk";
203 reg = <0x01c20060 0x14>;
204 clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
205 clock-names = "ahb1", "ahb2", "apb1", "apb2";
206 clock-indices = <5>, <6>, <8>,
225 clock-output-names = "bus_ce", "bus_dma", "bus_mmc0",
226 "bus_mmc1", "bus_mmc2", "bus_nand",
227 "bus_sdram", "bus_gmac", "bus_ts",
228 "bus_hstimer", "bus_spi0",
229 "bus_spi1", "bus_otg",
230 "bus_otg_ehci0", "bus_ehci1",
231 "bus_ehci2", "bus_ehci3",
232 "bus_otg_ohci0", "bus_ohci1",
233 "bus_ohci2", "bus_ohci3", "bus_ve",
234 "bus_lcd0", "bus_lcd1", "bus_deint",
235 "bus_csi", "bus_tve", "bus_hdmi",
236 "bus_de", "bus_gpu", "bus_msgbox",
237 "bus_spinlock", "bus_codec",
238 "bus_spdif", "bus_pio", "bus_ths",
239 "bus_i2s0", "bus_i2s1", "bus_i2s2",
240 "bus_i2c0", "bus_i2c1", "bus_i2c2",
241 "bus_uart0", "bus_uart1",
242 "bus_uart2", "bus_uart3",
243 "bus_scr", "bus_ephy", "bus_dbg";
246 mmc0_clk: clk@01c20088 {
248 compatible = "allwinner,sun4i-a10-mmc-clk";
249 reg = <0x01c20088 0x4>;
250 clocks = <&osc24M>, <&pll6 0>, <&pll8>;
251 clock-output-names = "mmc0",
256 mmc1_clk: clk@01c2008c {
258 compatible = "allwinner,sun4i-a10-mmc-clk";
259 reg = <0x01c2008c 0x4>;
260 clocks = <&osc24M>, <&pll6 0>, <&pll8>;
261 clock-output-names = "mmc1",
266 mmc2_clk: clk@01c20090 {
268 compatible = "allwinner,sun4i-a10-mmc-clk";
269 reg = <0x01c20090 0x4>;
270 clocks = <&osc24M>, <&pll6 0>, <&pll8>;
271 clock-output-names = "mmc2",
276 usb_clk: clk@01c200cc {
279 compatible = "allwinner,sun8i-h3-usb-clk";
280 reg = <0x01c200cc 0x4>;
282 clock-output-names = "usb_phy0", "usb_phy1",
283 "usb_phy2", "usb_phy3",
284 "usb_ohci0", "usb_ohci1",
285 "usb_ohci2", "usb_ohci3";
288 mbus_clk: clk@01c2015c {
290 compatible = "allwinner,sun8i-a23-mbus-clk";
291 reg = <0x01c2015c 0x4>;
292 clocks = <&osc24M>, <&pll6 1>, <&pll5>;
293 clock-output-names = "mbus";
297 compatible = "fixed-factor-clock";
302 clock-output-names = "apb0";
305 apb0_gates: clk@01f01428 {
306 compatible = "allwinner,sun8i-h3-apb0-gates-clk",
307 "allwinner,sun4i-a10-gates-clk";
308 reg = <0x01f01428 0x4>;
311 clock-indices = <0>, <1>;
312 clock-output-names = "apb0_pio", "apb0_ir";
315 ir_clk: ir_clk@01f01454 {
316 compatible = "allwinner,sun4i-a10-mod0-clk";
317 reg = <0x01f01454 0x4>;
319 clocks = <&osc32k>, <&osc24M>;
320 clock-output-names = "ir";
325 compatible = "simple-bus";
326 #address-cells = <1>;
330 dma: dma-controller@01c02000 {
331 compatible = "allwinner,sun8i-h3-dma";
332 reg = <0x01c02000 0x1000>;
333 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&bus_gates 6>;
335 resets = <&ahb_rst 6>;
340 compatible = "allwinner,sun5i-a13-mmc";
341 reg = <0x01c0f000 0x1000>;
342 clocks = <&bus_gates 8>,
350 resets = <&ahb_rst 8>;
352 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
354 #address-cells = <1>;
359 compatible = "allwinner,sun5i-a13-mmc";
360 reg = <0x01c10000 0x1000>;
361 clocks = <&bus_gates 9>,
369 resets = <&ahb_rst 9>;
371 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
373 #address-cells = <1>;
378 compatible = "allwinner,sun5i-a13-mmc";
379 reg = <0x01c11000 0x1000>;
380 clocks = <&bus_gates 10>,
388 resets = <&ahb_rst 10>;
390 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
392 #address-cells = <1>;
396 usbphy: phy@01c19400 {
397 compatible = "allwinner,sun8i-h3-usb-phy";
398 reg = <0x01c19400 0x2c>,
403 reg-names = "phy_ctrl",
408 clocks = <&usb_clk 8>,
412 clock-names = "usb0_phy",
416 resets = <&usb_clk 0>,
420 reset-names = "usb0_reset",
428 ehci1: usb@01c1b000 {
429 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
430 reg = <0x01c1b000 0x100>;
431 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&bus_gates 25>, <&bus_gates 29>;
433 resets = <&ahb_rst 25>, <&ahb_rst 29>;
439 ohci1: usb@01c1b400 {
440 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
441 reg = <0x01c1b400 0x100>;
442 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&bus_gates 29>, <&bus_gates 25>,
445 resets = <&ahb_rst 29>, <&ahb_rst 25>;
451 ehci2: usb@01c1c000 {
452 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
453 reg = <0x01c1c000 0x100>;
454 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&bus_gates 26>, <&bus_gates 30>;
456 resets = <&ahb_rst 26>, <&ahb_rst 30>;
462 ohci2: usb@01c1c400 {
463 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
464 reg = <0x01c1c400 0x100>;
465 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&bus_gates 30>, <&bus_gates 26>,
468 resets = <&ahb_rst 30>, <&ahb_rst 26>;
474 ehci3: usb@01c1d000 {
475 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
476 reg = <0x01c1d000 0x100>;
477 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
478 clocks = <&bus_gates 27>, <&bus_gates 31>;
479 resets = <&ahb_rst 27>, <&ahb_rst 31>;
485 ohci3: usb@01c1d400 {
486 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
487 reg = <0x01c1d400 0x100>;
488 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&bus_gates 31>, <&bus_gates 27>,
491 resets = <&ahb_rst 31>, <&ahb_rst 27>;
497 pio: pinctrl@01c20800 {
498 compatible = "allwinner,sun8i-h3-pinctrl";
499 reg = <0x01c20800 0x400>;
500 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
501 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&bus_gates 69>;
505 interrupt-controller;
506 #interrupt-cells = <3>;
508 rgmii_pins: rgmii_pins {
509 allwinner,pins = "PD0", "PD1", "PD2", "PD3",
511 "PD8", "PD9", "PD10",
512 "PD12", "PD13", "PD15",
514 allwinner,function = "emac";
515 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
516 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
519 uart0_pins_a: uart0@0 {
520 allwinner,pins = "PA4", "PA5";
521 allwinner,function = "uart0";
522 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
523 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
526 mmc0_pins_a: mmc0@0 {
527 allwinner,pins = "PF0", "PF1", "PF2", "PF3",
529 allwinner,function = "mmc0";
530 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
531 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
534 mmc0_cd_pin: mmc0_cd_pin@0 {
535 allwinner,pins = "PF6";
536 allwinner,function = "gpio_in";
537 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
538 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
541 mmc1_pins_a: mmc1@0 {
542 allwinner,pins = "PG0", "PG1", "PG2", "PG3",
544 allwinner,function = "mmc1";
545 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
546 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
549 mmc2_8bit_pins: mmc2_8bit {
550 allwinner,pins = "PC5", "PC6", "PC8",
551 "PC9", "PC10", "PC11",
552 "PC12", "PC13", "PC14",
554 allwinner,function = "mmc2";
555 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
556 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
560 ahb_rst: reset@01c202c0 {
562 compatible = "allwinner,sun6i-a31-ahb1-reset";
563 reg = <0x01c202c0 0xc>;
566 apb1_rst: reset@01c202d0 {
568 compatible = "allwinner,sun6i-a31-clock-reset";
569 reg = <0x01c202d0 0x4>;
572 apb2_rst: reset@01c202d8 {
574 compatible = "allwinner,sun6i-a31-clock-reset";
575 reg = <0x01c202d8 0x4>;
579 compatible = "allwinner,sun4i-a10-timer";
580 reg = <0x01c20c00 0xa0>;
581 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
582 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
586 wdt0: watchdog@01c20ca0 {
587 compatible = "allwinner,sun6i-a31-wdt";
588 reg = <0x01c20ca0 0x20>;
589 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
592 uart0: serial@01c28000 {
593 compatible = "snps,dw-apb-uart";
594 reg = <0x01c28000 0x400>;
595 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&bus_gates 112>;
599 resets = <&apb2_rst 16>;
600 dmas = <&dma 6>, <&dma 6>;
601 dma-names = "rx", "tx";
605 uart1: serial@01c28400 {
606 compatible = "snps,dw-apb-uart";
607 reg = <0x01c28400 0x400>;
608 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
611 clocks = <&bus_gates 113>;
612 resets = <&apb2_rst 17>;
613 dmas = <&dma 7>, <&dma 7>;
614 dma-names = "rx", "tx";
618 uart2: serial@01c28800 {
619 compatible = "snps,dw-apb-uart";
620 reg = <0x01c28800 0x400>;
621 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
624 clocks = <&bus_gates 114>;
625 resets = <&apb2_rst 18>;
626 dmas = <&dma 8>, <&dma 8>;
627 dma-names = "rx", "tx";
631 uart3: serial@01c28c00 {
632 compatible = "snps,dw-apb-uart";
633 reg = <0x01c28c00 0x400>;
634 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&bus_gates 115>;
638 resets = <&apb2_rst 19>;
639 dmas = <&dma 9>, <&dma 9>;
640 dma-names = "rx", "tx";
644 emac: ethernet@01c30000 {
645 compatible = "allwinner,sun8i-h3-emac";
646 reg = <0x01c30000 0x2000>, <0x01c00030 0x4>;
647 reg-names = "emac", "syscon";
648 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
649 resets = <&ahb_rst 17>, <&ahb_rst 66>;
650 reset-names = "ahb", "ephy";
651 clocks = <&bus_gates 17>, <&bus_gates 128>;
652 clock-names = "ahb", "ephy";
653 #address-cells = <1>;
658 gic: interrupt-controller@01c81000 {
659 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
660 reg = <0x01c81000 0x1000>,
664 interrupt-controller;
665 #interrupt-cells = <3>;
666 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
670 compatible = "allwinner,sun6i-a31-rtc";
671 reg = <0x01f00000 0x54>;
672 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
673 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
676 apb0_reset: reset@01f014b0 {
677 reg = <0x01f014b0 0x4>;
678 compatible = "allwinner,sun6i-a31-clock-reset";
683 compatible = "allwinner,sun5i-a13-ir";
684 clocks = <&apb0_gates 1>, <&ir_clk>;
685 clock-names = "apb", "ir";
686 resets = <&apb0_reset 1>;
687 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
688 reg = <0x01f02000 0x40>;
692 r_pio: pinctrl@01f02c00 {
693 compatible = "allwinner,sun8i-h3-r-pinctrl";
694 reg = <0x01f02c00 0x400>;
695 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
696 clocks = <&apb0_gates 0>;
697 resets = <&apb0_reset 0>;
700 interrupt-controller;
701 #interrupt-cells = <3>;
704 allwinner,pins = "PL11";
705 allwinner,function = "s_cir_rx";
706 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
707 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;