2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include "sun8i-a23-a33.dtsi"
46 #include <dt-bindings/thermal/thermal.h>
49 cpu0_opp_table: opp_table0 {
50 compatible = "operating-points-v2";
54 opp-hz = /bits/ 64 <120000000>;
55 opp-microvolt = <1040000>;
56 clock-latency-ns = <244144>; /* 8 32k periods */
60 opp-hz = /bits/ 64 <240000000>;
61 opp-microvolt = <1040000>;
62 clock-latency-ns = <244144>; /* 8 32k periods */
66 opp-hz = /bits/ 64 <312000000>;
67 opp-microvolt = <1040000>;
68 clock-latency-ns = <244144>; /* 8 32k periods */
72 opp-hz = /bits/ 64 <408000000>;
73 opp-microvolt = <1040000>;
74 clock-latency-ns = <244144>; /* 8 32k periods */
78 opp-hz = /bits/ 64 <480000000>;
79 opp-microvolt = <1040000>;
80 clock-latency-ns = <244144>; /* 8 32k periods */
84 opp-hz = /bits/ 64 <504000000>;
85 opp-microvolt = <1040000>;
86 clock-latency-ns = <244144>; /* 8 32k periods */
90 opp-hz = /bits/ 64 <600000000>;
91 opp-microvolt = <1040000>;
92 clock-latency-ns = <244144>; /* 8 32k periods */
96 opp-hz = /bits/ 64 <648000000>;
97 opp-microvolt = <1040000>;
98 clock-latency-ns = <244144>; /* 8 32k periods */
102 opp-hz = /bits/ 64 <720000000>;
103 opp-microvolt = <1100000>;
104 clock-latency-ns = <244144>; /* 8 32k periods */
108 opp-hz = /bits/ 64 <816000000>;
109 opp-microvolt = <1100000>;
110 clock-latency-ns = <244144>; /* 8 32k periods */
114 opp-hz = /bits/ 64 <912000000>;
115 opp-microvolt = <1200000>;
116 clock-latency-ns = <244144>; /* 8 32k periods */
120 opp-hz = /bits/ 64 <1008000000>;
121 opp-microvolt = <1200000>;
122 clock-latency-ns = <244144>; /* 8 32k periods */
128 clocks = <&ccu CLK_CPUX>;
130 operating-points-v2 = <&cpu0_opp_table>;
131 #cooling-cells = <2>;
135 operating-points-v2 = <&cpu0_opp_table>;
139 compatible = "arm,cortex-a7";
142 operating-points-v2 = <&cpu0_opp_table>;
146 compatible = "arm,cortex-a7";
149 operating-points-v2 = <&cpu0_opp_table>;
154 compatible = "allwinner,sun8i-a33-display-engine";
155 allwinner,pipelines = <&fe0>;
160 compatible = "iio-hwmon";
161 io-channels = <&ths>;
164 mali_opp_table: gpu-opp-table {
165 compatible = "operating-points-v2";
168 opp-hz = /bits/ 64 <144000000>;
172 opp-hz = /bits/ 64 <240000000>;
176 opp-hz = /bits/ 64 <384000000>;
181 reg = <0x40000000 0x80000000>;
185 compatible = "simple-audio-card";
186 simple-audio-card,name = "sun8i-a33-audio";
187 simple-audio-card,format = "i2s";
188 simple-audio-card,frame-master = <&link_codec>;
189 simple-audio-card,bitclock-master = <&link_codec>;
190 simple-audio-card,mclk-fs = <512>;
191 simple-audio-card,aux-devs = <&codec_analog>;
192 simple-audio-card,routing =
193 "Left DAC", "AIF1 Slot 0 Left",
194 "Right DAC", "AIF1 Slot 0 Right";
197 simple-audio-card,cpu {
201 link_codec: simple-audio-card,codec {
202 sound-dai = <&codec>;
207 tcon0: lcd-controller@1c0c000 {
208 compatible = "allwinner,sun8i-a33-tcon";
209 reg = <0x01c0c000 0x1000>;
210 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&ccu CLK_BUS_LCD>,
215 clock-output-names = "tcon-pixel-clock";
216 resets = <&ccu RST_BUS_LCD>;
221 #address-cells = <1>;
225 #address-cells = <1>;
229 tcon0_in_drc0: endpoint@0 {
231 remote-endpoint = <&drc0_out_tcon0>;
236 #address-cells = <1>;
240 tcon0_out_dsi: endpoint@1 {
242 remote-endpoint = <&dsi_in_tcon0>;
248 crypto: crypto-engine@1c15000 {
249 compatible = "allwinner,sun4i-a10-crypto";
250 reg = <0x01c15000 0x1000>;
251 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
253 clock-names = "ahb", "mod";
254 resets = <&ccu RST_BUS_SS>;
259 #sound-dai-cells = <0>;
260 compatible = "allwinner,sun6i-a31-i2s";
261 reg = <0x01c22c00 0x200>;
262 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
263 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
264 clock-names = "apb", "mod";
265 resets = <&ccu RST_BUS_CODEC>;
266 dmas = <&dma 15>, <&dma 15>;
267 dma-names = "rx", "tx";
271 codec: codec@1c22e00 {
272 #sound-dai-cells = <0>;
273 compatible = "allwinner,sun8i-a33-codec";
274 reg = <0x01c22e00 0x400>;
275 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
276 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
277 clock-names = "bus", "mod";
282 compatible = "allwinner,sun8i-a33-ths";
283 reg = <0x01c25000 0x100>;
284 #thermal-sensor-cells = <0>;
285 #io-channel-cells = <0>;
289 compatible = "allwinner,sun6i-a31-mipi-dsi";
290 reg = <0x01ca0000 0x1000>;
291 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&ccu CLK_BUS_MIPI_DSI>,
294 clock-names = "bus", "mod";
295 resets = <&ccu RST_BUS_MIPI_DSI>;
301 #address-cells = <1>;
305 #address-cells = <1>;
309 dsi_in_tcon0: endpoint {
310 remote-endpoint = <&tcon0_out_dsi>;
316 dphy: d-phy@1ca1000 {
317 compatible = "allwinner,sun6i-a31-mipi-dphy";
318 reg = <0x01ca1000 0x1000>;
319 clocks = <&ccu CLK_BUS_MIPI_DSI>,
321 clock-names = "bus", "mod";
322 resets = <&ccu RST_BUS_MIPI_DSI>;
327 fe0: display-frontend@1e00000 {
328 compatible = "allwinner,sun8i-a33-display-frontend";
329 reg = <0x01e00000 0x20000>;
330 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
332 <&ccu CLK_DRAM_DE_FE>;
333 clock-names = "ahb", "mod",
335 resets = <&ccu RST_BUS_DE_FE>;
338 #address-cells = <1>;
342 #address-cells = <1>;
346 fe0_out_be0: endpoint@0 {
348 remote-endpoint = <&be0_in_fe0>;
354 be0: display-backend@1e60000 {
355 compatible = "allwinner,sun8i-a33-display-backend";
356 reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
357 reg-names = "be", "sat";
358 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
360 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
361 clock-names = "ahb", "mod",
363 resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
364 reset-names = "be", "sat";
365 assigned-clocks = <&ccu CLK_DE_BE>;
366 assigned-clock-rates = <300000000>;
369 #address-cells = <1>;
373 #address-cells = <1>;
377 be0_in_fe0: endpoint@0 {
379 remote-endpoint = <&fe0_out_be0>;
384 #address-cells = <1>;
388 be0_out_drc0: endpoint@0 {
390 remote-endpoint = <&drc0_in_be0>;
397 compatible = "allwinner,sun8i-a33-drc";
398 reg = <0x01e70000 0x10000>;
399 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
402 clock-names = "ahb", "mod", "ram";
403 resets = <&ccu RST_BUS_DRC>;
405 assigned-clocks = <&ccu CLK_DRC>;
406 assigned-clock-rates = <300000000>;
409 #address-cells = <1>;
413 #address-cells = <1>;
417 drc0_in_be0: endpoint@0 {
419 remote-endpoint = <&be0_out_drc0>;
424 #address-cells = <1>;
428 drc0_out_tcon0: endpoint@0 {
430 remote-endpoint = <&tcon0_in_drc0>;
440 polling-delay-passive = <250>;
441 polling-delay = <1000>;
442 thermal-sensors = <&ths>;
446 trip = <&cpu_alert0>;
447 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
450 trip = <&cpu_alert1>;
451 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
455 trip = <&gpu_alert0>;
456 cooling-device = <&mali 1 THERMAL_NO_LIMIT>;
460 trip = <&gpu_alert1>;
461 cooling-device = <&mali 2 THERMAL_NO_LIMIT>;
466 cpu_alert0: cpu_alert0 {
468 temperature = <75000>;
473 gpu_alert0: gpu_alert0 {
475 temperature = <85000>;
480 cpu_alert1: cpu_alert1 {
482 temperature = <90000>;
487 gpu_alert1: gpu_alert1 {
489 temperature = <95000>;
496 temperature = <110000>;
506 compatible = "allwinner,sun8i-a33-ccu";
510 operating-points-v2 = <&mali_opp_table>;
514 compatible = "allwinner,sun8i-a33-pinctrl";
515 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
518 uart0_pins_b: uart0@1 {
526 compatible = "allwinner,sun8i-a33-musb";
530 compatible = "allwinner,sun8i-a33-usb-phy";
531 reg = <0x01c19400 0x14>, <0x01c1a800 0x4>;
532 reg-names = "phy_ctrl", "pmu1";