2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include "skeleton.dtsi"
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
49 #include <dt-bindings/dma/sun4i-a10.h>
50 #include <dt-bindings/clock/sun7i-a20-ccu.h>
51 #include <dt-bindings/reset/sun4i-a10-ccu.h>
54 interrupt-parent = <&gic>;
66 compatible = "allwinner,simple-framebuffer",
68 allwinner,pipeline = "de_be0-lcd0-hdmi";
69 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
70 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
71 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>,
77 compatible = "allwinner,simple-framebuffer",
79 allwinner,pipeline = "de_be0-lcd0";
80 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
81 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>,
82 <&ccu CLK_DRAM_DE_BE0>;
87 compatible = "allwinner,simple-framebuffer",
89 allwinner,pipeline = "de_be0-lcd0-tve0";
90 clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
91 <&ccu CLK_AHB_DE_BE0>,
92 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>,
93 <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>;
103 compatible = "arm,cortex-a7";
106 clocks = <&ccu CLK_CPU>;
107 clock-latency = <244144>; /* 8 32k periods */
118 #cooling-cells = <2>;
122 compatible = "arm,cortex-a7";
131 polling-delay-passive = <250>;
132 polling-delay = <1000>;
133 thermal-sensors = <&rtp>;
137 trip = <&cpu_alert0>;
138 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
143 cpu_alert0: cpu_alert0 {
145 temperature = <75000>;
152 temperature = <100000>;
161 reg = <0x40000000 0x80000000>;
165 compatible = "arm,armv7-timer";
166 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
167 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
168 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
169 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
173 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
174 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
179 #address-cells = <1>;
183 osc24M: clk@1c20050 {
185 compatible = "fixed-clock";
186 clock-frequency = <24000000>;
187 clock-output-names = "osc24M";
192 compatible = "fixed-clock";
193 clock-frequency = <32768>;
194 clock-output-names = "osc32k";
198 * The following two are dummy clocks, placeholders
199 * used in the gmac_tx clock. The gmac driver will
200 * choose one parent depending on the PHY interface
201 * mode, using clk_set_rate auto-reparenting.
203 * The actual TX clock rate is not controlled by the
206 mii_phy_tx_clk: clk@1 {
208 compatible = "fixed-clock";
209 clock-frequency = <25000000>;
210 clock-output-names = "mii_phy_tx";
213 gmac_int_tx_clk: clk@2 {
215 compatible = "fixed-clock";
216 clock-frequency = <125000000>;
217 clock-output-names = "gmac_int_tx";
220 gmac_tx_clk: clk@1c20164 {
222 compatible = "allwinner,sun7i-a20-gmac-clk";
223 reg = <0x01c20164 0x4>;
224 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
225 clock-output-names = "gmac_tx";
231 compatible = "allwinner,sun7i-a20-display-engine";
232 allwinner,pipelines = <&fe0>, <&fe1>;
237 compatible = "simple-bus";
238 #address-cells = <1>;
242 sram-controller@1c00000 {
243 compatible = "allwinner,sun4i-a10-sram-controller";
244 reg = <0x01c00000 0x30>;
245 #address-cells = <1>;
250 compatible = "mmio-sram";
251 reg = <0x00000000 0xc000>;
252 #address-cells = <1>;
254 ranges = <0 0x00000000 0xc000>;
256 emac_sram: sram-section@8000 {
257 compatible = "allwinner,sun4i-a10-sram-a3-a4";
258 reg = <0x8000 0x4000>;
264 compatible = "mmio-sram";
265 reg = <0x00010000 0x1000>;
266 #address-cells = <1>;
268 ranges = <0 0x00010000 0x1000>;
270 otg_sram: sram-section@0 {
271 compatible = "allwinner,sun4i-a10-sram-d";
272 reg = <0x0000 0x1000>;
278 nmi_intc: interrupt-controller@1c00030 {
279 compatible = "allwinner,sun7i-a20-sc-nmi";
280 interrupt-controller;
281 #interrupt-cells = <2>;
282 reg = <0x01c00030 0x0c>;
283 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
286 dma: dma-controller@1c02000 {
287 compatible = "allwinner,sun4i-a10-dma";
288 reg = <0x01c02000 0x1000>;
289 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&ccu CLK_AHB_DMA>;
295 compatible = "allwinner,sun4i-a10-nand";
296 reg = <0x01c03000 0x1000>;
297 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
299 clock-names = "ahb", "mod";
300 dmas = <&dma SUN4I_DMA_DEDICATED 3>;
303 #address-cells = <1>;
308 compatible = "allwinner,sun4i-a10-spi";
309 reg = <0x01c05000 0x1000>;
310 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
312 clock-names = "ahb", "mod";
313 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
314 <&dma SUN4I_DMA_DEDICATED 26>;
315 dma-names = "rx", "tx";
317 #address-cells = <1>;
323 compatible = "allwinner,sun4i-a10-spi";
324 reg = <0x01c06000 0x1000>;
325 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
327 clock-names = "ahb", "mod";
328 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
329 <&dma SUN4I_DMA_DEDICATED 8>;
330 dma-names = "rx", "tx";
332 #address-cells = <1>;
337 emac: ethernet@1c0b000 {
338 compatible = "allwinner,sun4i-a10-emac";
339 reg = <0x01c0b000 0x1000>;
340 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&ccu CLK_AHB_EMAC>;
342 allwinner,sram = <&emac_sram 1>;
347 compatible = "allwinner,sun4i-a10-mdio";
348 reg = <0x01c0b080 0x14>;
350 #address-cells = <1>;
354 tcon0: lcd-controller@1c0c000 {
355 compatible = "allwinner,sun7i-a20-tcon";
356 reg = <0x01c0c000 0x1000>;
357 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
358 resets = <&ccu RST_TCON0>;
360 clocks = <&ccu CLK_AHB_LCD0>,
361 <&ccu CLK_TCON0_CH0>,
362 <&ccu CLK_TCON0_CH1>;
366 clock-output-names = "tcon0-pixel-clock";
367 dmas = <&dma SUN4I_DMA_DEDICATED 14>;
370 #address-cells = <1>;
374 #address-cells = <1>;
378 tcon0_in_be0: endpoint@0 {
380 remote-endpoint = <&be0_out_tcon0>;
383 tcon0_in_be1: endpoint@1 {
385 remote-endpoint = <&be1_out_tcon0>;
390 #address-cells = <1>;
394 tcon0_out_hdmi: endpoint@1 {
396 remote-endpoint = <&hdmi_in_tcon0>;
397 allwinner,tcon-channel = <1>;
403 tcon1: lcd-controller@1c0d000 {
404 compatible = "allwinner,sun7i-a20-tcon";
405 reg = <0x01c0d000 0x1000>;
406 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
407 resets = <&ccu RST_TCON1>;
409 clocks = <&ccu CLK_AHB_LCD1>,
410 <&ccu CLK_TCON1_CH0>,
411 <&ccu CLK_TCON1_CH1>;
415 clock-output-names = "tcon1-pixel-clock";
416 dmas = <&dma SUN4I_DMA_DEDICATED 15>;
419 #address-cells = <1>;
423 #address-cells = <1>;
427 tcon1_in_be0: endpoint@0 {
429 remote-endpoint = <&be0_out_tcon1>;
432 tcon1_in_be1: endpoint@1 {
434 remote-endpoint = <&be1_out_tcon1>;
439 #address-cells = <1>;
443 tcon1_out_hdmi: endpoint@1 {
445 remote-endpoint = <&hdmi_in_tcon1>;
446 allwinner,tcon-channel = <1>;
453 compatible = "allwinner,sun7i-a20-mmc";
454 reg = <0x01c0f000 0x1000>;
455 clocks = <&ccu CLK_AHB_MMC0>,
457 <&ccu CLK_MMC0_OUTPUT>,
458 <&ccu CLK_MMC0_SAMPLE>;
463 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
465 #address-cells = <1>;
470 compatible = "allwinner,sun7i-a20-mmc";
471 reg = <0x01c10000 0x1000>;
472 clocks = <&ccu CLK_AHB_MMC1>,
474 <&ccu CLK_MMC1_OUTPUT>,
475 <&ccu CLK_MMC1_SAMPLE>;
480 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
482 #address-cells = <1>;
487 compatible = "allwinner,sun7i-a20-mmc";
488 reg = <0x01c11000 0x1000>;
489 clocks = <&ccu CLK_AHB_MMC2>,
491 <&ccu CLK_MMC2_OUTPUT>,
492 <&ccu CLK_MMC2_SAMPLE>;
497 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
499 #address-cells = <1>;
504 compatible = "allwinner,sun7i-a20-mmc";
505 reg = <0x01c12000 0x1000>;
506 clocks = <&ccu CLK_AHB_MMC3>,
508 <&ccu CLK_MMC3_OUTPUT>,
509 <&ccu CLK_MMC3_SAMPLE>;
514 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
516 #address-cells = <1>;
520 usb_otg: usb@1c13000 {
521 compatible = "allwinner,sun4i-a10-musb";
522 reg = <0x01c13000 0x0400>;
523 clocks = <&ccu CLK_AHB_OTG>;
524 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
525 interrupt-names = "mc";
528 extcon = <&usbphy 0>;
529 allwinner,sram = <&otg_sram 1>;
533 usbphy: phy@1c13400 {
535 compatible = "allwinner,sun7i-a20-usb-phy";
536 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
537 reg-names = "phy_ctrl", "pmu1", "pmu2";
538 clocks = <&ccu CLK_USB_PHY>;
539 clock-names = "usb_phy";
540 resets = <&ccu RST_USB_PHY0>,
543 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
548 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
549 reg = <0x01c14000 0x100>;
550 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&ccu CLK_AHB_EHCI0>;
558 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
559 reg = <0x01c14400 0x100>;
560 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
567 crypto: crypto-engine@1c15000 {
568 compatible = "allwinner,sun7i-a20-crypto",
569 "allwinner,sun4i-a10-crypto";
570 reg = <0x01c15000 0x1000>;
571 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
573 clock-names = "ahb", "mod";
577 compatible = "allwinner,sun7i-a20-hdmi",
578 "allwinner,sun5i-a10s-hdmi";
579 reg = <0x01c16000 0x1000>;
580 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
581 clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
582 <&ccu CLK_PLL_VIDEO0_2X>,
583 <&ccu CLK_PLL_VIDEO1_2X>;
584 clock-names = "ahb", "mod", "pll-0", "pll-1";
585 dmas = <&dma SUN4I_DMA_NORMAL 16>,
586 <&dma SUN4I_DMA_NORMAL 16>,
587 <&dma SUN4I_DMA_DEDICATED 24>;
588 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
592 #address-cells = <1>;
596 #address-cells = <1>;
600 hdmi_in_tcon0: endpoint@0 {
602 remote-endpoint = <&tcon0_out_hdmi>;
605 hdmi_in_tcon1: endpoint@1 {
607 remote-endpoint = <&tcon1_out_hdmi>;
612 #address-cells = <1>;
620 compatible = "allwinner,sun4i-a10-spi";
621 reg = <0x01c17000 0x1000>;
622 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
624 clock-names = "ahb", "mod";
625 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
626 <&dma SUN4I_DMA_DEDICATED 28>;
627 dma-names = "rx", "tx";
629 #address-cells = <1>;
635 compatible = "allwinner,sun4i-a10-ahci";
636 reg = <0x01c18000 0x1000>;
637 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
638 clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
643 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
644 reg = <0x01c1c000 0x100>;
645 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&ccu CLK_AHB_EHCI1>;
653 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
654 reg = <0x01c1c400 0x100>;
655 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
663 compatible = "allwinner,sun4i-a10-spi";
664 reg = <0x01c1f000 0x1000>;
665 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
667 clock-names = "ahb", "mod";
668 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
669 <&dma SUN4I_DMA_DEDICATED 30>;
670 dma-names = "rx", "tx";
672 #address-cells = <1>;
678 compatible = "allwinner,sun7i-a20-ccu";
679 reg = <0x01c20000 0x400>;
680 clocks = <&osc24M>, <&osc32k>;
681 clock-names = "hosc", "losc";
686 pio: pinctrl@1c20800 {
687 compatible = "allwinner,sun7i-a20-pinctrl";
688 reg = <0x01c20800 0x400>;
689 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
691 clock-names = "apb", "hosc", "losc";
693 interrupt-controller;
694 #interrupt-cells = <3>;
697 can0_pins_a: can0@0 {
698 pins = "PH20", "PH21";
702 clk_out_a_pins_a: clk_out_a@0 {
704 function = "clk_out_a";
707 clk_out_b_pins_a: clk_out_b@0 {
709 function = "clk_out_b";
712 emac_pins_a: emac0@0 {
713 pins = "PA0", "PA1", "PA2",
714 "PA3", "PA4", "PA5", "PA6",
715 "PA7", "PA8", "PA9", "PA10",
716 "PA11", "PA12", "PA13", "PA14",
721 gmac_pins_mii_a: gmac_mii@0 {
722 pins = "PA0", "PA1", "PA2",
723 "PA3", "PA4", "PA5", "PA6",
724 "PA7", "PA8", "PA9", "PA10",
725 "PA11", "PA12", "PA13", "PA14",
730 gmac_pins_rgmii_a: gmac_rgmii@0 {
731 pins = "PA0", "PA1", "PA2",
732 "PA3", "PA4", "PA5", "PA6",
733 "PA7", "PA8", "PA10",
734 "PA11", "PA12", "PA13",
738 * data lines in RGMII mode use DDR mode
739 * and need a higher signal drive strength
741 drive-strength = <40>;
744 i2c0_pins_a: i2c0@0 {
749 i2c1_pins_a: i2c1@0 {
750 pins = "PB18", "PB19";
754 i2c2_pins_a: i2c2@0 {
755 pins = "PB20", "PB21";
759 i2c3_pins_a: i2c3@0 {
764 ir0_rx_pins_a: ir0@0 {
769 ir0_tx_pins_a: ir0@1 {
774 ir1_rx_pins_a: ir1@0 {
779 ir1_tx_pins_a: ir1@1 {
784 mmc0_pins_a: mmc0@0 {
785 pins = "PF0", "PF1", "PF2",
788 drive-strength = <30>;
792 mmc2_pins_a: mmc2@0 {
793 pins = "PC6", "PC7", "PC8",
794 "PC9", "PC10", "PC11";
796 drive-strength = <30>;
800 mmc3_pins_a: mmc3@0 {
801 pins = "PI4", "PI5", "PI6",
804 drive-strength = <30>;
808 ps20_pins_a: ps20@0 {
809 pins = "PI20", "PI21";
813 ps21_pins_a: ps21@0 {
814 pins = "PH12", "PH13";
818 pwm0_pins_a: pwm0@0 {
823 pwm1_pins_a: pwm1@0 {
828 spdif_tx_pins_a: spdif@0 {
834 spi0_pins_a: spi0@0 {
835 pins = "PI11", "PI12", "PI13";
839 spi0_cs0_pins_a: spi0_cs0@0 {
844 spi0_cs1_pins_a: spi0_cs1@0 {
849 spi1_pins_a: spi1@0 {
850 pins = "PI17", "PI18", "PI19";
854 spi1_cs0_pins_a: spi1_cs0@0 {
859 spi2_pins_a: spi2@0 {
860 pins = "PC20", "PC21", "PC22";
864 spi2_pins_b: spi2@1 {
865 pins = "PB15", "PB16", "PB17";
869 spi2_cs0_pins_a: spi2_cs0@0 {
874 spi2_cs0_pins_b: spi2_cs0@1 {
879 uart0_pins_a: uart0@0 {
880 pins = "PB22", "PB23";
884 uart2_pins_a: uart2@0 {
885 pins = "PI16", "PI17", "PI18", "PI19";
889 uart3_pins_a: uart3@0 {
890 pins = "PG6", "PG7", "PG8", "PG9";
894 uart3_pins_b: uart3@1 {
899 uart4_pins_a: uart4@0 {
900 pins = "PG10", "PG11";
904 uart4_pins_b: uart4@1 {
909 uart5_pins_a: uart5@0 {
910 pins = "PI10", "PI11";
914 uart6_pins_a: uart6@0 {
915 pins = "PI12", "PI13";
919 uart7_pins_a: uart7@0 {
920 pins = "PI20", "PI21";
926 compatible = "allwinner,sun4i-a10-timer";
927 reg = <0x01c20c00 0x90>;
928 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
929 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
930 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
933 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
937 wdt: watchdog@1c20c90 {
938 compatible = "allwinner,sun4i-a10-wdt";
939 reg = <0x01c20c90 0x10>;
943 compatible = "allwinner,sun7i-a20-rtc";
944 reg = <0x01c20d00 0x20>;
945 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
949 compatible = "allwinner,sun7i-a20-pwm";
950 reg = <0x01c20e00 0xc>;
956 spdif: spdif@1c21000 {
957 #sound-dai-cells = <0>;
958 compatible = "allwinner,sun4i-a10-spdif";
959 reg = <0x01c21000 0x400>;
960 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
961 clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
962 clock-names = "apb", "spdif";
963 dmas = <&dma SUN4I_DMA_NORMAL 2>,
964 <&dma SUN4I_DMA_NORMAL 2>;
965 dma-names = "rx", "tx";
970 compatible = "allwinner,sun4i-a10-ir";
971 clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
972 clock-names = "apb", "ir";
973 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
974 reg = <0x01c21800 0x40>;
979 compatible = "allwinner,sun4i-a10-ir";
980 clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
981 clock-names = "apb", "ir";
982 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
983 reg = <0x01c21c00 0x40>;
988 #sound-dai-cells = <0>;
989 compatible = "allwinner,sun4i-a10-i2s";
990 reg = <0x01c22000 0x400>;
991 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
992 clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>;
993 clock-names = "apb", "mod";
994 dmas = <&dma SUN4I_DMA_NORMAL 4>,
995 <&dma SUN4I_DMA_NORMAL 4>;
996 dma-names = "rx", "tx";
1001 #sound-dai-cells = <0>;
1002 compatible = "allwinner,sun4i-a10-i2s";
1003 reg = <0x01c22400 0x400>;
1004 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1005 clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
1006 clock-names = "apb", "mod";
1007 dmas = <&dma SUN4I_DMA_NORMAL 3>,
1008 <&dma SUN4I_DMA_NORMAL 3>;
1009 dma-names = "rx", "tx";
1010 status = "disabled";
1013 lradc: lradc@1c22800 {
1014 compatible = "allwinner,sun4i-a10-lradc-keys";
1015 reg = <0x01c22800 0x100>;
1016 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1017 status = "disabled";
1020 codec: codec@1c22c00 {
1021 #sound-dai-cells = <0>;
1022 compatible = "allwinner,sun7i-a20-codec";
1023 reg = <0x01c22c00 0x40>;
1024 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1025 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
1026 clock-names = "apb", "codec";
1027 dmas = <&dma SUN4I_DMA_NORMAL 19>,
1028 <&dma SUN4I_DMA_NORMAL 19>;
1029 dma-names = "rx", "tx";
1030 status = "disabled";
1033 sid: eeprom@1c23800 {
1034 compatible = "allwinner,sun7i-a20-sid";
1035 reg = <0x01c23800 0x200>;
1039 #sound-dai-cells = <0>;
1040 compatible = "allwinner,sun4i-a10-i2s";
1041 reg = <0x01c24400 0x400>;
1042 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1043 clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>;
1044 clock-names = "apb", "mod";
1045 dmas = <&dma SUN4I_DMA_NORMAL 6>,
1046 <&dma SUN4I_DMA_NORMAL 6>;
1047 dma-names = "rx", "tx";
1048 status = "disabled";
1052 compatible = "allwinner,sun5i-a13-ts";
1053 reg = <0x01c25000 0x100>;
1054 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1055 #thermal-sensor-cells = <0>;
1058 uart0: serial@1c28000 {
1059 compatible = "snps,dw-apb-uart";
1060 reg = <0x01c28000 0x400>;
1061 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1064 clocks = <&ccu CLK_APB1_UART0>;
1065 status = "disabled";
1068 uart1: serial@1c28400 {
1069 compatible = "snps,dw-apb-uart";
1070 reg = <0x01c28400 0x400>;
1071 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1074 clocks = <&ccu CLK_APB1_UART1>;
1075 status = "disabled";
1078 uart2: serial@1c28800 {
1079 compatible = "snps,dw-apb-uart";
1080 reg = <0x01c28800 0x400>;
1081 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1084 clocks = <&ccu CLK_APB1_UART2>;
1085 status = "disabled";
1088 uart3: serial@1c28c00 {
1089 compatible = "snps,dw-apb-uart";
1090 reg = <0x01c28c00 0x400>;
1091 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1094 clocks = <&ccu CLK_APB1_UART3>;
1095 status = "disabled";
1098 uart4: serial@1c29000 {
1099 compatible = "snps,dw-apb-uart";
1100 reg = <0x01c29000 0x400>;
1101 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1104 clocks = <&ccu CLK_APB1_UART4>;
1105 status = "disabled";
1108 uart5: serial@1c29400 {
1109 compatible = "snps,dw-apb-uart";
1110 reg = <0x01c29400 0x400>;
1111 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1114 clocks = <&ccu CLK_APB1_UART5>;
1115 status = "disabled";
1118 uart6: serial@1c29800 {
1119 compatible = "snps,dw-apb-uart";
1120 reg = <0x01c29800 0x400>;
1121 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1124 clocks = <&ccu CLK_APB1_UART6>;
1125 status = "disabled";
1128 uart7: serial@1c29c00 {
1129 compatible = "snps,dw-apb-uart";
1130 reg = <0x01c29c00 0x400>;
1131 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1134 clocks = <&ccu CLK_APB1_UART7>;
1135 status = "disabled";
1139 compatible = "allwinner,sun4i-a10-ps2";
1140 reg = <0x01c2a000 0x400>;
1141 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1142 clocks = <&ccu CLK_APB1_PS20>;
1143 status = "disabled";
1147 compatible = "allwinner,sun4i-a10-ps2";
1148 reg = <0x01c2a400 0x400>;
1149 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1150 clocks = <&ccu CLK_APB1_PS21>;
1151 status = "disabled";
1155 compatible = "allwinner,sun7i-a20-i2c",
1156 "allwinner,sun4i-a10-i2c";
1157 reg = <0x01c2ac00 0x400>;
1158 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1159 clocks = <&ccu CLK_APB1_I2C0>;
1160 status = "disabled";
1161 #address-cells = <1>;
1166 compatible = "allwinner,sun7i-a20-i2c",
1167 "allwinner,sun4i-a10-i2c";
1168 reg = <0x01c2b000 0x400>;
1169 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1170 clocks = <&ccu CLK_APB1_I2C1>;
1171 status = "disabled";
1172 #address-cells = <1>;
1177 compatible = "allwinner,sun7i-a20-i2c",
1178 "allwinner,sun4i-a10-i2c";
1179 reg = <0x01c2b400 0x400>;
1180 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1181 clocks = <&ccu CLK_APB1_I2C2>;
1182 status = "disabled";
1183 #address-cells = <1>;
1188 compatible = "allwinner,sun7i-a20-i2c",
1189 "allwinner,sun4i-a10-i2c";
1190 reg = <0x01c2b800 0x400>;
1191 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1192 clocks = <&ccu CLK_APB1_I2C3>;
1193 status = "disabled";
1194 #address-cells = <1>;
1199 compatible = "allwinner,sun7i-a20-can",
1200 "allwinner,sun4i-a10-can";
1201 reg = <0x01c2bc00 0x400>;
1202 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1203 clocks = <&ccu CLK_APB1_CAN>;
1204 status = "disabled";
1208 compatible = "allwinner,sun7i-a20-i2c",
1209 "allwinner,sun4i-a10-i2c";
1210 reg = <0x01c2c000 0x400>;
1211 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1212 clocks = <&ccu CLK_APB1_I2C4>;
1213 status = "disabled";
1214 #address-cells = <1>;
1219 compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
1220 reg = <0x01c40000 0x10000>;
1221 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1222 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1223 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1224 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
1225 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
1226 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1227 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1228 interrupt-names = "gp",
1235 clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
1236 clock-names = "bus", "core";
1237 resets = <&ccu RST_GPU>;
1239 assigned-clocks = <&ccu CLK_GPU>;
1240 assigned-clock-rates = <384000000>;
1243 gmac: ethernet@1c50000 {
1244 compatible = "allwinner,sun7i-a20-gmac";
1245 reg = <0x01c50000 0x10000>;
1246 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1247 interrupt-names = "macirq";
1248 clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>;
1249 clock-names = "stmmaceth", "allwinner_gmac_tx";
1252 snps,force_sf_dma_mode;
1253 status = "disabled";
1254 #address-cells = <1>;
1259 compatible = "allwinner,sun7i-a20-hstimer";
1260 reg = <0x01c60000 0x1000>;
1261 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1262 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1263 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1264 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1265 clocks = <&ccu CLK_AHB_HSTIMER>;
1268 gic: interrupt-controller@1c81000 {
1269 compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1270 reg = <0x01c81000 0x1000>,
1271 <0x01c82000 0x2000>,
1272 <0x01c84000 0x2000>,
1273 <0x01c86000 0x2000>;
1274 interrupt-controller;
1275 #interrupt-cells = <3>;
1276 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1279 fe0: display-frontend@1e00000 {
1280 compatible = "allwinner,sun7i-a20-display-frontend";
1281 reg = <0x01e00000 0x20000>;
1282 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1283 clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1284 <&ccu CLK_DRAM_DE_FE0>;
1285 clock-names = "ahb", "mod",
1287 resets = <&ccu RST_DE_FE0>;
1290 #address-cells = <1>;
1294 #address-cells = <1>;
1298 fe0_out_be0: endpoint@0 {
1300 remote-endpoint = <&be0_in_fe0>;
1303 fe0_out_be1: endpoint@1 {
1305 remote-endpoint = <&be1_in_fe0>;
1311 fe1: display-frontend@1e20000 {
1312 compatible = "allwinner,sun7i-a20-display-frontend";
1313 reg = <0x01e20000 0x20000>;
1314 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1315 clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1316 <&ccu CLK_DRAM_DE_FE1>;
1317 clock-names = "ahb", "mod",
1319 resets = <&ccu RST_DE_FE1>;
1322 #address-cells = <1>;
1326 #address-cells = <1>;
1330 fe1_out_be0: endpoint@0 {
1332 remote-endpoint = <&be0_in_fe1>;
1335 fe1_out_be1: endpoint@1 {
1337 remote-endpoint = <&be1_in_fe1>;
1343 be1: display-backend@1e40000 {
1344 compatible = "allwinner,sun7i-a20-display-backend";
1345 reg = <0x01e40000 0x10000>;
1346 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1347 clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1348 <&ccu CLK_DRAM_DE_BE1>;
1349 clock-names = "ahb", "mod",
1351 resets = <&ccu RST_DE_BE1>;
1354 #address-cells = <1>;
1358 #address-cells = <1>;
1362 be1_in_fe0: endpoint@0 {
1364 remote-endpoint = <&fe0_out_be1>;
1367 be1_in_fe1: endpoint@1 {
1369 remote-endpoint = <&fe1_out_be1>;
1374 #address-cells = <1>;
1378 be1_out_tcon0: endpoint@0 {
1380 remote-endpoint = <&tcon0_in_be1>;
1383 be1_out_tcon1: endpoint@1 {
1385 remote-endpoint = <&tcon1_in_be1>;
1391 be0: display-backend@1e60000 {
1392 compatible = "allwinner,sun7i-a20-display-backend";
1393 reg = <0x01e60000 0x10000>;
1394 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1395 clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1396 <&ccu CLK_DRAM_DE_BE0>;
1397 clock-names = "ahb", "mod",
1399 resets = <&ccu RST_DE_BE0>;
1402 #address-cells = <1>;
1406 #address-cells = <1>;
1410 be0_in_fe0: endpoint@0 {
1412 remote-endpoint = <&fe0_out_be0>;
1415 be0_in_fe1: endpoint@1 {
1417 remote-endpoint = <&fe1_out_be0>;
1422 #address-cells = <1>;
1426 be0_out_tcon0: endpoint@0 {
1428 remote-endpoint = <&tcon0_in_be0>;
1431 be0_out_tcon1: endpoint@1 {
1433 remote-endpoint = <&tcon1_in_be0>;