2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/dma/sun4i-a10.h>
48 #include <dt-bindings/clock/sun7i-a20-ccu.h>
49 #include <dt-bindings/reset/sun4i-a10-ccu.h>
52 interrupt-parent = <&gic>;
65 framebuffer-lcd0-hdmi {
66 compatible = "allwinner,simple-framebuffer",
68 allwinner,pipeline = "de_be0-lcd0-hdmi";
69 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
70 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
71 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>,
77 compatible = "allwinner,simple-framebuffer",
79 allwinner,pipeline = "de_be0-lcd0";
80 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
81 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>,
82 <&ccu CLK_DRAM_DE_BE0>;
86 framebuffer-lcd0-tve0 {
87 compatible = "allwinner,simple-framebuffer",
89 allwinner,pipeline = "de_be0-lcd0-tve0";
90 clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
91 <&ccu CLK_AHB_DE_BE0>,
92 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>,
93 <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>;
103 compatible = "arm,cortex-a7";
106 clocks = <&ccu CLK_CPU>;
107 clock-latency = <244144>; /* 8 32k periods */
118 #cooling-cells = <2>;
122 compatible = "arm,cortex-a7";
125 clocks = <&ccu CLK_CPU>;
126 clock-latency = <244144>; /* 8 32k periods */
137 #cooling-cells = <2>;
144 polling-delay-passive = <250>;
145 polling-delay = <1000>;
146 thermal-sensors = <&rtp>;
150 trip = <&cpu_alert0>;
151 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
152 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
157 cpu_alert0: cpu_alert0 {
159 temperature = <75000>;
166 temperature = <100000>;
175 #address-cells = <1>;
179 /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
181 compatible = "shared-dma-pool";
183 alloc-ranges = <0x4a000000 0x6000000>;
190 compatible = "arm,armv7-timer";
191 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
192 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
193 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
194 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
198 compatible = "arm,cortex-a7-pmu";
199 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
204 #address-cells = <1>;
210 compatible = "fixed-clock";
211 clock-frequency = <24000000>;
212 clock-output-names = "osc24M";
217 compatible = "fixed-clock";
218 clock-frequency = <32768>;
219 clock-output-names = "osc32k";
223 * The following two are dummy clocks, placeholders
224 * used in the gmac_tx clock. The gmac driver will
225 * choose one parent depending on the PHY interface
226 * mode, using clk_set_rate auto-reparenting.
228 * The actual TX clock rate is not controlled by the
231 mii_phy_tx_clk: clk-mii-phy-tx {
233 compatible = "fixed-clock";
234 clock-frequency = <25000000>;
235 clock-output-names = "mii_phy_tx";
238 gmac_int_tx_clk: clk-gmac-int-tx {
240 compatible = "fixed-clock";
241 clock-frequency = <125000000>;
242 clock-output-names = "gmac_int_tx";
245 gmac_tx_clk: clk@1c20164 {
247 compatible = "allwinner,sun7i-a20-gmac-clk";
248 reg = <0x01c20164 0x4>;
249 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
250 clock-output-names = "gmac_tx";
256 compatible = "allwinner,sun7i-a20-display-engine";
257 allwinner,pipelines = <&fe0>, <&fe1>;
262 compatible = "simple-bus";
263 #address-cells = <1>;
267 system-control@1c00000 {
268 compatible = "allwinner,sun7i-a20-system-control",
269 "allwinner,sun4i-a10-system-control";
270 reg = <0x01c00000 0x30>;
271 #address-cells = <1>;
276 compatible = "mmio-sram";
277 reg = <0x00000000 0xc000>;
278 #address-cells = <1>;
280 ranges = <0 0x00000000 0xc000>;
282 emac_sram: sram-section@8000 {
283 compatible = "allwinner,sun7i-a20-sram-a3-a4",
284 "allwinner,sun4i-a10-sram-a3-a4";
285 reg = <0x8000 0x4000>;
291 compatible = "mmio-sram";
292 reg = <0x00010000 0x1000>;
293 #address-cells = <1>;
295 ranges = <0 0x00010000 0x1000>;
297 otg_sram: sram-section@0 {
298 compatible = "allwinner,sun7i-a20-sram-d",
299 "allwinner,sun4i-a10-sram-d";
300 reg = <0x0000 0x1000>;
305 sram_c: sram@1d00000 {
306 compatible = "mmio-sram";
307 reg = <0x01d00000 0xd0000>;
308 #address-cells = <1>;
310 ranges = <0 0x01d00000 0xd0000>;
312 ve_sram: sram-section@0 {
313 compatible = "allwinner,sun7i-a20-sram-c1",
314 "allwinner,sun4i-a10-sram-c1";
315 reg = <0x000000 0x80000>;
320 nmi_intc: interrupt-controller@1c00030 {
321 compatible = "allwinner,sun7i-a20-sc-nmi";
322 interrupt-controller;
323 #interrupt-cells = <2>;
324 reg = <0x01c00030 0x0c>;
325 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
328 dma: dma-controller@1c02000 {
329 compatible = "allwinner,sun4i-a10-dma";
330 reg = <0x01c02000 0x1000>;
331 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&ccu CLK_AHB_DMA>;
337 compatible = "allwinner,sun4i-a10-nand";
338 reg = <0x01c03000 0x1000>;
339 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
341 clock-names = "ahb", "mod";
342 dmas = <&dma SUN4I_DMA_DEDICATED 3>;
345 #address-cells = <1>;
350 compatible = "allwinner,sun4i-a10-spi";
351 reg = <0x01c05000 0x1000>;
352 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
354 clock-names = "ahb", "mod";
355 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
356 <&dma SUN4I_DMA_DEDICATED 26>;
357 dma-names = "rx", "tx";
359 #address-cells = <1>;
365 compatible = "allwinner,sun4i-a10-spi";
366 reg = <0x01c06000 0x1000>;
367 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
369 clock-names = "ahb", "mod";
370 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
371 <&dma SUN4I_DMA_DEDICATED 8>;
372 dma-names = "rx", "tx";
374 #address-cells = <1>;
379 emac: ethernet@1c0b000 {
380 compatible = "allwinner,sun4i-a10-emac";
381 reg = <0x01c0b000 0x1000>;
382 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&ccu CLK_AHB_EMAC>;
384 allwinner,sram = <&emac_sram 1>;
389 compatible = "allwinner,sun4i-a10-mdio";
390 reg = <0x01c0b080 0x14>;
392 #address-cells = <1>;
396 tcon0: lcd-controller@1c0c000 {
397 compatible = "allwinner,sun7i-a20-tcon";
398 reg = <0x01c0c000 0x1000>;
399 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
400 resets = <&ccu RST_TCON0>;
402 clocks = <&ccu CLK_AHB_LCD0>,
403 <&ccu CLK_TCON0_CH0>,
404 <&ccu CLK_TCON0_CH1>;
408 clock-output-names = "tcon0-pixel-clock";
409 dmas = <&dma SUN4I_DMA_DEDICATED 14>;
412 #address-cells = <1>;
416 #address-cells = <1>;
420 tcon0_in_be0: endpoint@0 {
422 remote-endpoint = <&be0_out_tcon0>;
425 tcon0_in_be1: endpoint@1 {
427 remote-endpoint = <&be1_out_tcon0>;
432 #address-cells = <1>;
436 tcon0_out_hdmi: endpoint@1 {
438 remote-endpoint = <&hdmi_in_tcon0>;
439 allwinner,tcon-channel = <1>;
445 tcon1: lcd-controller@1c0d000 {
446 compatible = "allwinner,sun7i-a20-tcon";
447 reg = <0x01c0d000 0x1000>;
448 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
449 resets = <&ccu RST_TCON1>;
451 clocks = <&ccu CLK_AHB_LCD1>,
452 <&ccu CLK_TCON1_CH0>,
453 <&ccu CLK_TCON1_CH1>;
457 clock-output-names = "tcon1-pixel-clock";
458 dmas = <&dma SUN4I_DMA_DEDICATED 15>;
461 #address-cells = <1>;
465 #address-cells = <1>;
469 tcon1_in_be0: endpoint@0 {
471 remote-endpoint = <&be0_out_tcon1>;
474 tcon1_in_be1: endpoint@1 {
476 remote-endpoint = <&be1_out_tcon1>;
481 #address-cells = <1>;
485 tcon1_out_hdmi: endpoint@1 {
487 remote-endpoint = <&hdmi_in_tcon1>;
488 allwinner,tcon-channel = <1>;
494 video-codec@1c0e000 {
495 compatible = "allwinner,sun7i-a20-video-engine";
496 reg = <0x01c0e000 0x1000>;
497 clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
499 clock-names = "ahb", "mod", "ram";
500 resets = <&ccu RST_VE>;
501 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
502 allwinner,sram = <&ve_sram 1>;
506 compatible = "allwinner,sun7i-a20-mmc";
507 reg = <0x01c0f000 0x1000>;
508 clocks = <&ccu CLK_AHB_MMC0>,
510 <&ccu CLK_MMC0_OUTPUT>,
511 <&ccu CLK_MMC0_SAMPLE>;
516 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
517 pinctrl-names = "default";
518 pinctrl-0 = <&mmc0_pins>;
520 #address-cells = <1>;
525 compatible = "allwinner,sun7i-a20-mmc";
526 reg = <0x01c10000 0x1000>;
527 clocks = <&ccu CLK_AHB_MMC1>,
529 <&ccu CLK_MMC1_OUTPUT>,
530 <&ccu CLK_MMC1_SAMPLE>;
535 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
537 #address-cells = <1>;
542 compatible = "allwinner,sun7i-a20-mmc";
543 reg = <0x01c11000 0x1000>;
544 clocks = <&ccu CLK_AHB_MMC2>,
546 <&ccu CLK_MMC2_OUTPUT>,
547 <&ccu CLK_MMC2_SAMPLE>;
552 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
553 pinctrl-names = "default";
554 pinctrl-0 = <&mmc2_pins>;
556 #address-cells = <1>;
561 compatible = "allwinner,sun7i-a20-mmc";
562 reg = <0x01c12000 0x1000>;
563 clocks = <&ccu CLK_AHB_MMC3>,
565 <&ccu CLK_MMC3_OUTPUT>,
566 <&ccu CLK_MMC3_SAMPLE>;
571 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
572 pinctrl-names = "default";
573 pinctrl-0 = <&mmc3_pins>;
575 #address-cells = <1>;
579 usb_otg: usb@1c13000 {
580 compatible = "allwinner,sun4i-a10-musb";
581 reg = <0x01c13000 0x0400>;
582 clocks = <&ccu CLK_AHB_OTG>;
583 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
584 interrupt-names = "mc";
587 extcon = <&usbphy 0>;
588 allwinner,sram = <&otg_sram 1>;
592 usbphy: phy@1c13400 {
594 compatible = "allwinner,sun7i-a20-usb-phy";
595 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
596 reg-names = "phy_ctrl", "pmu1", "pmu2";
597 clocks = <&ccu CLK_USB_PHY>;
598 clock-names = "usb_phy";
599 resets = <&ccu RST_USB_PHY0>,
602 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
607 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
608 reg = <0x01c14000 0x100>;
609 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&ccu CLK_AHB_EHCI0>;
617 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
618 reg = <0x01c14400 0x100>;
619 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
626 crypto: crypto-engine@1c15000 {
627 compatible = "allwinner,sun7i-a20-crypto",
628 "allwinner,sun4i-a10-crypto";
629 reg = <0x01c15000 0x1000>;
630 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
632 clock-names = "ahb", "mod";
636 compatible = "allwinner,sun7i-a20-hdmi",
637 "allwinner,sun5i-a10s-hdmi";
638 reg = <0x01c16000 0x1000>;
639 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
640 clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
641 <&ccu CLK_PLL_VIDEO0_2X>,
642 <&ccu CLK_PLL_VIDEO1_2X>;
643 clock-names = "ahb", "mod", "pll-0", "pll-1";
644 dmas = <&dma SUN4I_DMA_NORMAL 16>,
645 <&dma SUN4I_DMA_NORMAL 16>,
646 <&dma SUN4I_DMA_DEDICATED 24>;
647 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
651 #address-cells = <1>;
655 #address-cells = <1>;
659 hdmi_in_tcon0: endpoint@0 {
661 remote-endpoint = <&tcon0_out_hdmi>;
664 hdmi_in_tcon1: endpoint@1 {
666 remote-endpoint = <&tcon1_out_hdmi>;
677 compatible = "allwinner,sun4i-a10-spi";
678 reg = <0x01c17000 0x1000>;
679 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
680 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
681 clock-names = "ahb", "mod";
682 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
683 <&dma SUN4I_DMA_DEDICATED 28>;
684 dma-names = "rx", "tx";
686 #address-cells = <1>;
692 compatible = "allwinner,sun4i-a10-ahci";
693 reg = <0x01c18000 0x1000>;
694 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
695 clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
700 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
701 reg = <0x01c1c000 0x100>;
702 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&ccu CLK_AHB_EHCI1>;
710 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
711 reg = <0x01c1c400 0x100>;
712 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
720 compatible = "allwinner,sun4i-a10-spi";
721 reg = <0x01c1f000 0x1000>;
722 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
723 clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
724 clock-names = "ahb", "mod";
725 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
726 <&dma SUN4I_DMA_DEDICATED 30>;
727 dma-names = "rx", "tx";
729 #address-cells = <1>;
735 compatible = "allwinner,sun7i-a20-ccu";
736 reg = <0x01c20000 0x400>;
737 clocks = <&osc24M>, <&osc32k>;
738 clock-names = "hosc", "losc";
743 pio: pinctrl@1c20800 {
744 compatible = "allwinner,sun7i-a20-pinctrl";
745 reg = <0x01c20800 0x400>;
746 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
747 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
748 clock-names = "apb", "hosc", "losc";
750 interrupt-controller;
751 #interrupt-cells = <3>;
754 can_ph_pins: can-ph-pins {
755 pins = "PH20", "PH21";
759 clk_out_a_pin: clk-out-a-pin {
761 function = "clk_out_a";
764 clk_out_b_pin: clk-out-b-pin {
766 function = "clk_out_b";
769 emac_pa_pins: emac-pa-pins {
770 pins = "PA0", "PA1", "PA2",
771 "PA3", "PA4", "PA5", "PA6",
772 "PA7", "PA8", "PA9", "PA10",
773 "PA11", "PA12", "PA13", "PA14",
778 gmac_mii_pins: gmac-mii-pins {
779 pins = "PA0", "PA1", "PA2",
780 "PA3", "PA4", "PA5", "PA6",
781 "PA7", "PA8", "PA9", "PA10",
782 "PA11", "PA12", "PA13", "PA14",
787 gmac_rgmii_pins: gmac-rgmii-pins {
788 pins = "PA0", "PA1", "PA2",
789 "PA3", "PA4", "PA5", "PA6",
790 "PA7", "PA8", "PA10",
791 "PA11", "PA12", "PA13",
795 * data lines in RGMII mode use DDR mode
796 * and need a higher signal drive strength
798 drive-strength = <40>;
801 i2c0_pins: i2c0-pins {
806 i2c1_pins: i2c1-pins {
807 pins = "PB18", "PB19";
811 i2c2_pins: i2c2-pins {
812 pins = "PB20", "PB21";
816 i2c3_pins: i2c3-pins {
821 ir0_rx_pin: ir0-rx-pin {
826 ir0_tx_pin: ir0-tx-pin {
831 ir1_rx_pin: ir1-rx-pin {
836 ir1_tx_pin: ir1-tx-pin {
841 mmc0_pins: mmc0-pins {
842 pins = "PF0", "PF1", "PF2",
845 drive-strength = <30>;
849 mmc2_pins: mmc2-pins {
850 pins = "PC6", "PC7", "PC8",
851 "PC9", "PC10", "PC11";
853 drive-strength = <30>;
857 mmc3_pins: mmc3-pins {
858 pins = "PI4", "PI5", "PI6",
861 drive-strength = <30>;
865 ps2_0_pins: ps2-0-pins {
866 pins = "PI20", "PI21";
870 ps2_1_ph_pins: ps2-1-ph-pins {
871 pins = "PH12", "PH13";
885 spdif_tx_pin: spdif-tx-pin {
891 spi0_pi_pins: spi0-pi-pins {
892 pins = "PI11", "PI12", "PI13";
896 spi0_cs0_pi_pin: spi0-cs0-pi-pin {
901 spi0_cs1_pi_pin: spi0-cs1-pi-pin {
906 spi1_pi_pins: spi1-pi-pins {
907 pins = "PI17", "PI18", "PI19";
911 spi1_cs0_pi_pin: spi1-cs0-pi-pin {
916 spi2_pb_pins: spi2-pb-pins {
917 pins = "PB15", "PB16", "PB17";
921 spi2_cs0_pb_pin: spi2-cs0-pb-pin {
926 spi2_pc_pins: spi2-pc-pins {
927 pins = "PC20", "PC21", "PC22";
931 spi2_cs0_pc_pin: spi2-cs0-pc-pin {
936 uart0_pb_pins: uart0-pb-pins {
937 pins = "PB22", "PB23";
941 uart2_pi_pins: uart2-pi-pins {
942 pins = "PI18", "PI19";
946 uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins {
947 pins = "PI16", "PI17";
951 uart3_pg_pins: uart3-pg-pins {
956 uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
961 uart3_ph_pins: uart3-ph-pins {
966 uart4_pg_pins: uart4-pg-pins {
967 pins = "PG10", "PG11";
971 uart4_ph_pins: uart4-ph-pins {
976 uart5_pi_pins: uart5-pi-pins {
977 pins = "PI10", "PI11";
981 uart6_pi_pins: uart6-pi-pins {
982 pins = "PI12", "PI13";
986 uart7_pi_pins: uart7-pi-pins {
987 pins = "PI20", "PI21";
993 compatible = "allwinner,sun4i-a10-timer";
994 reg = <0x01c20c00 0x90>;
995 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
996 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
997 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
998 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
999 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
1000 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1004 wdt: watchdog@1c20c90 {
1005 compatible = "allwinner,sun4i-a10-wdt";
1006 reg = <0x01c20c90 0x10>;
1010 compatible = "allwinner,sun7i-a20-rtc";
1011 reg = <0x01c20d00 0x20>;
1012 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1016 compatible = "allwinner,sun7i-a20-pwm";
1017 reg = <0x01c20e00 0xc>;
1020 status = "disabled";
1023 spdif: spdif@1c21000 {
1024 #sound-dai-cells = <0>;
1025 compatible = "allwinner,sun4i-a10-spdif";
1026 reg = <0x01c21000 0x400>;
1027 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1028 clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
1029 clock-names = "apb", "spdif";
1030 dmas = <&dma SUN4I_DMA_NORMAL 2>,
1031 <&dma SUN4I_DMA_NORMAL 2>;
1032 dma-names = "rx", "tx";
1033 status = "disabled";
1037 compatible = "allwinner,sun4i-a10-ir";
1038 clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
1039 clock-names = "apb", "ir";
1040 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1041 reg = <0x01c21800 0x40>;
1042 status = "disabled";
1046 compatible = "allwinner,sun4i-a10-ir";
1047 clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
1048 clock-names = "apb", "ir";
1049 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1050 reg = <0x01c21c00 0x40>;
1051 status = "disabled";
1055 #sound-dai-cells = <0>;
1056 compatible = "allwinner,sun4i-a10-i2s";
1057 reg = <0x01c22000 0x400>;
1058 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1059 clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>;
1060 clock-names = "apb", "mod";
1061 dmas = <&dma SUN4I_DMA_NORMAL 4>,
1062 <&dma SUN4I_DMA_NORMAL 4>;
1063 dma-names = "rx", "tx";
1064 status = "disabled";
1068 #sound-dai-cells = <0>;
1069 compatible = "allwinner,sun4i-a10-i2s";
1070 reg = <0x01c22400 0x400>;
1071 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1072 clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
1073 clock-names = "apb", "mod";
1074 dmas = <&dma SUN4I_DMA_NORMAL 3>,
1075 <&dma SUN4I_DMA_NORMAL 3>;
1076 dma-names = "rx", "tx";
1077 status = "disabled";
1080 lradc: lradc@1c22800 {
1081 compatible = "allwinner,sun4i-a10-lradc-keys";
1082 reg = <0x01c22800 0x100>;
1083 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1084 status = "disabled";
1087 codec: codec@1c22c00 {
1088 #sound-dai-cells = <0>;
1089 compatible = "allwinner,sun7i-a20-codec";
1090 reg = <0x01c22c00 0x40>;
1091 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1092 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
1093 clock-names = "apb", "codec";
1094 dmas = <&dma SUN4I_DMA_NORMAL 19>,
1095 <&dma SUN4I_DMA_NORMAL 19>;
1096 dma-names = "rx", "tx";
1097 status = "disabled";
1100 sid: eeprom@1c23800 {
1101 compatible = "allwinner,sun7i-a20-sid";
1102 reg = <0x01c23800 0x200>;
1106 #sound-dai-cells = <0>;
1107 compatible = "allwinner,sun4i-a10-i2s";
1108 reg = <0x01c24400 0x400>;
1109 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1110 clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>;
1111 clock-names = "apb", "mod";
1112 dmas = <&dma SUN4I_DMA_NORMAL 6>,
1113 <&dma SUN4I_DMA_NORMAL 6>;
1114 dma-names = "rx", "tx";
1115 status = "disabled";
1119 compatible = "allwinner,sun5i-a13-ts";
1120 reg = <0x01c25000 0x100>;
1121 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1122 #thermal-sensor-cells = <0>;
1125 uart0: serial@1c28000 {
1126 compatible = "snps,dw-apb-uart";
1127 reg = <0x01c28000 0x400>;
1128 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1131 clocks = <&ccu CLK_APB1_UART0>;
1132 status = "disabled";
1135 uart1: serial@1c28400 {
1136 compatible = "snps,dw-apb-uart";
1137 reg = <0x01c28400 0x400>;
1138 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1141 clocks = <&ccu CLK_APB1_UART1>;
1142 status = "disabled";
1145 uart2: serial@1c28800 {
1146 compatible = "snps,dw-apb-uart";
1147 reg = <0x01c28800 0x400>;
1148 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1151 clocks = <&ccu CLK_APB1_UART2>;
1152 status = "disabled";
1155 uart3: serial@1c28c00 {
1156 compatible = "snps,dw-apb-uart";
1157 reg = <0x01c28c00 0x400>;
1158 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1161 clocks = <&ccu CLK_APB1_UART3>;
1162 status = "disabled";
1165 uart4: serial@1c29000 {
1166 compatible = "snps,dw-apb-uart";
1167 reg = <0x01c29000 0x400>;
1168 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1171 clocks = <&ccu CLK_APB1_UART4>;
1172 status = "disabled";
1175 uart5: serial@1c29400 {
1176 compatible = "snps,dw-apb-uart";
1177 reg = <0x01c29400 0x400>;
1178 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1181 clocks = <&ccu CLK_APB1_UART5>;
1182 status = "disabled";
1185 uart6: serial@1c29800 {
1186 compatible = "snps,dw-apb-uart";
1187 reg = <0x01c29800 0x400>;
1188 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1191 clocks = <&ccu CLK_APB1_UART6>;
1192 status = "disabled";
1195 uart7: serial@1c29c00 {
1196 compatible = "snps,dw-apb-uart";
1197 reg = <0x01c29c00 0x400>;
1198 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1201 clocks = <&ccu CLK_APB1_UART7>;
1202 status = "disabled";
1206 compatible = "allwinner,sun4i-a10-ps2";
1207 reg = <0x01c2a000 0x400>;
1208 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1209 clocks = <&ccu CLK_APB1_PS20>;
1210 status = "disabled";
1214 compatible = "allwinner,sun4i-a10-ps2";
1215 reg = <0x01c2a400 0x400>;
1216 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1217 clocks = <&ccu CLK_APB1_PS21>;
1218 status = "disabled";
1222 compatible = "allwinner,sun7i-a20-i2c",
1223 "allwinner,sun4i-a10-i2c";
1224 reg = <0x01c2ac00 0x400>;
1225 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1226 clocks = <&ccu CLK_APB1_I2C0>;
1227 pinctrl-names = "default";
1228 pinctrl-0 = <&i2c0_pins>;
1229 status = "disabled";
1230 #address-cells = <1>;
1235 compatible = "allwinner,sun7i-a20-i2c",
1236 "allwinner,sun4i-a10-i2c";
1237 reg = <0x01c2b000 0x400>;
1238 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1239 clocks = <&ccu CLK_APB1_I2C1>;
1240 pinctrl-names = "default";
1241 pinctrl-0 = <&i2c1_pins>;
1242 status = "disabled";
1243 #address-cells = <1>;
1248 compatible = "allwinner,sun7i-a20-i2c",
1249 "allwinner,sun4i-a10-i2c";
1250 reg = <0x01c2b400 0x400>;
1251 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1252 clocks = <&ccu CLK_APB1_I2C2>;
1253 pinctrl-names = "default";
1254 pinctrl-0 = <&i2c2_pins>;
1255 status = "disabled";
1256 #address-cells = <1>;
1261 compatible = "allwinner,sun7i-a20-i2c",
1262 "allwinner,sun4i-a10-i2c";
1263 reg = <0x01c2b800 0x400>;
1264 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1265 clocks = <&ccu CLK_APB1_I2C3>;
1266 pinctrl-names = "default";
1267 pinctrl-0 = <&i2c3_pins>;
1268 status = "disabled";
1269 #address-cells = <1>;
1274 compatible = "allwinner,sun7i-a20-can",
1275 "allwinner,sun4i-a10-can";
1276 reg = <0x01c2bc00 0x400>;
1277 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1278 clocks = <&ccu CLK_APB1_CAN>;
1279 status = "disabled";
1283 compatible = "allwinner,sun7i-a20-i2c",
1284 "allwinner,sun4i-a10-i2c";
1285 reg = <0x01c2c000 0x400>;
1286 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1287 clocks = <&ccu CLK_APB1_I2C4>;
1288 status = "disabled";
1289 #address-cells = <1>;
1294 compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
1295 reg = <0x01c40000 0x10000>;
1296 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1297 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1298 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1299 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
1300 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
1301 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1302 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1303 interrupt-names = "gp",
1310 clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
1311 clock-names = "bus", "core";
1312 resets = <&ccu RST_GPU>;
1314 assigned-clocks = <&ccu CLK_GPU>;
1315 assigned-clock-rates = <384000000>;
1318 gmac: ethernet@1c50000 {
1319 compatible = "allwinner,sun7i-a20-gmac";
1320 reg = <0x01c50000 0x10000>;
1321 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1322 interrupt-names = "macirq";
1323 clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>;
1324 clock-names = "stmmaceth", "allwinner_gmac_tx";
1327 snps,force_sf_dma_mode;
1328 status = "disabled";
1329 #address-cells = <1>;
1334 compatible = "allwinner,sun7i-a20-hstimer";
1335 reg = <0x01c60000 0x1000>;
1336 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1340 clocks = <&ccu CLK_AHB_HSTIMER>;
1343 gic: interrupt-controller@1c81000 {
1344 compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1345 reg = <0x01c81000 0x1000>,
1346 <0x01c82000 0x2000>,
1347 <0x01c84000 0x2000>,
1348 <0x01c86000 0x2000>;
1349 interrupt-controller;
1350 #interrupt-cells = <3>;
1351 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1354 fe0: display-frontend@1e00000 {
1355 compatible = "allwinner,sun7i-a20-display-frontend";
1356 reg = <0x01e00000 0x20000>;
1357 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1358 clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1359 <&ccu CLK_DRAM_DE_FE0>;
1360 clock-names = "ahb", "mod",
1362 resets = <&ccu RST_DE_FE0>;
1365 #address-cells = <1>;
1369 #address-cells = <1>;
1373 fe0_out_be0: endpoint@0 {
1375 remote-endpoint = <&be0_in_fe0>;
1378 fe0_out_be1: endpoint@1 {
1380 remote-endpoint = <&be1_in_fe0>;
1386 fe1: display-frontend@1e20000 {
1387 compatible = "allwinner,sun7i-a20-display-frontend";
1388 reg = <0x01e20000 0x20000>;
1389 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1390 clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1391 <&ccu CLK_DRAM_DE_FE1>;
1392 clock-names = "ahb", "mod",
1394 resets = <&ccu RST_DE_FE1>;
1397 #address-cells = <1>;
1401 #address-cells = <1>;
1405 fe1_out_be0: endpoint@0 {
1407 remote-endpoint = <&be0_in_fe1>;
1410 fe1_out_be1: endpoint@1 {
1412 remote-endpoint = <&be1_in_fe1>;
1418 be1: display-backend@1e40000 {
1419 compatible = "allwinner,sun7i-a20-display-backend";
1420 reg = <0x01e40000 0x10000>;
1421 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1422 clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1423 <&ccu CLK_DRAM_DE_BE1>;
1424 clock-names = "ahb", "mod",
1426 resets = <&ccu RST_DE_BE1>;
1429 #address-cells = <1>;
1433 #address-cells = <1>;
1437 be1_in_fe0: endpoint@0 {
1439 remote-endpoint = <&fe0_out_be1>;
1442 be1_in_fe1: endpoint@1 {
1444 remote-endpoint = <&fe1_out_be1>;
1449 #address-cells = <1>;
1453 be1_out_tcon0: endpoint@0 {
1455 remote-endpoint = <&tcon0_in_be1>;
1458 be1_out_tcon1: endpoint@1 {
1460 remote-endpoint = <&tcon1_in_be1>;
1466 be0: display-backend@1e60000 {
1467 compatible = "allwinner,sun7i-a20-display-backend";
1468 reg = <0x01e60000 0x10000>;
1469 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1470 clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1471 <&ccu CLK_DRAM_DE_BE0>;
1472 clock-names = "ahb", "mod",
1474 resets = <&ccu RST_DE_BE0>;
1477 #address-cells = <1>;
1481 #address-cells = <1>;
1485 be0_in_fe0: endpoint@0 {
1487 remote-endpoint = <&fe0_out_be0>;
1490 be0_in_fe1: endpoint@1 {
1492 remote-endpoint = <&fe1_out_be0>;
1497 #address-cells = <1>;
1501 be0_out_tcon0: endpoint@0 {
1503 remote-endpoint = <&tcon0_in_be0>;
1506 be0_out_tcon1: endpoint@1 {
1508 remote-endpoint = <&tcon1_in_be0>;