2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include "skeleton.dtsi"
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
50 #include <dt-bindings/clock/sun6i-a31-ccu.h>
51 #include <dt-bindings/reset/sun6i-a31-ccu.h>
54 interrupt-parent = <&gic>;
65 simplefb_hdmi: framebuffer@0 {
66 compatible = "allwinner,simple-framebuffer",
68 allwinner,pipeline = "de_be0-lcd0-hdmi";
69 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
70 <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
71 <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
72 <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
76 simplefb_lcd: framebuffer@1 {
77 compatible = "allwinner,simple-framebuffer",
79 allwinner,pipeline = "de_be0-lcd0";
80 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
81 <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
82 <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
88 compatible = "arm,armv7-timer";
89 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
90 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
93 clock-frequency = <24000000>;
94 arm,cpu-registers-not-fw-configured;
98 enable-method = "allwinner,sun6i-a31";
103 compatible = "arm,cortex-a7";
106 clocks = <&ccu CLK_CPU>;
107 clock-latency = <244144>; /* 8 32k periods */
115 #cooling-cells = <2>;
119 compatible = "arm,cortex-a7";
125 compatible = "arm,cortex-a7";
131 compatible = "arm,cortex-a7";
140 polling-delay-passive = <250>;
141 polling-delay = <1000>;
142 thermal-sensors = <&rtp>;
146 trip = <&cpu_alert0>;
147 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
152 cpu_alert0: cpu_alert0 {
154 temperature = <70000>;
161 temperature = <100000>;
170 reg = <0x40000000 0x80000000>;
174 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
175 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
182 #address-cells = <1>;
188 compatible = "fixed-clock";
189 clock-frequency = <24000000>;
194 compatible = "fixed-clock";
195 clock-frequency = <32768>;
196 clock-output-names = "osc32k";
200 * The following two are dummy clocks, placeholders
201 * used in the gmac_tx clock. The gmac driver will
202 * choose one parent depending on the PHY interface
203 * mode, using clk_set_rate auto-reparenting.
205 * The actual TX clock rate is not controlled by the
208 mii_phy_tx_clk: clk@1 {
210 compatible = "fixed-clock";
211 clock-frequency = <25000000>;
212 clock-output-names = "mii_phy_tx";
215 gmac_int_tx_clk: clk@2 {
217 compatible = "fixed-clock";
218 clock-frequency = <125000000>;
219 clock-output-names = "gmac_int_tx";
222 gmac_tx_clk: clk@1c200d0 {
224 compatible = "allwinner,sun7i-a20-gmac-clk";
225 reg = <0x01c200d0 0x4>;
226 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
227 clock-output-names = "gmac_tx";
232 compatible = "allwinner,sun6i-a31-display-engine";
233 allwinner,pipelines = <&fe0>, <&fe1>;
238 compatible = "simple-bus";
239 #address-cells = <1>;
243 dma: dma-controller@1c02000 {
244 compatible = "allwinner,sun6i-a31-dma";
245 reg = <0x01c02000 0x1000>;
246 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&ccu CLK_AHB1_DMA>;
248 resets = <&ccu RST_AHB1_DMA>;
252 tcon0: lcd-controller@1c0c000 {
253 compatible = "allwinner,sun6i-a31-tcon";
254 reg = <0x01c0c000 0x1000>;
255 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
256 resets = <&ccu RST_AHB1_LCD0>;
258 clocks = <&ccu CLK_AHB1_LCD0>,
264 clock-output-names = "tcon0-pixel-clock";
267 #address-cells = <1>;
271 #address-cells = <1>;
275 tcon0_in_drc0: endpoint@0 {
277 remote-endpoint = <&drc0_out_tcon0>;
280 tcon0_in_drc1: endpoint@1 {
282 remote-endpoint = <&drc1_out_tcon0>;
287 #address-cells = <1>;
291 tcon0_out_hdmi: endpoint@1 {
293 remote-endpoint = <&hdmi_in_tcon0>;
294 allwinner,tcon-channel = <1>;
300 tcon1: lcd-controller@1c0d000 {
301 compatible = "allwinner,sun6i-a31-tcon";
302 reg = <0x01c0d000 0x1000>;
303 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
304 resets = <&ccu RST_AHB1_LCD1>;
306 clocks = <&ccu CLK_AHB1_LCD1>,
312 clock-output-names = "tcon1-pixel-clock";
315 #address-cells = <1>;
319 #address-cells = <1>;
323 tcon1_in_drc0: endpoint@0 {
325 remote-endpoint = <&drc0_out_tcon1>;
328 tcon1_in_drc1: endpoint@1 {
330 remote-endpoint = <&drc1_out_tcon1>;
335 #address-cells = <1>;
339 tcon1_out_hdmi: endpoint@1 {
341 remote-endpoint = <&hdmi_in_tcon1>;
342 allwinner,tcon-channel = <1>;
349 compatible = "allwinner,sun7i-a20-mmc";
350 reg = <0x01c0f000 0x1000>;
351 clocks = <&ccu CLK_AHB1_MMC0>,
353 <&ccu CLK_MMC0_OUTPUT>,
354 <&ccu CLK_MMC0_SAMPLE>;
359 resets = <&ccu RST_AHB1_MMC0>;
361 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
363 #address-cells = <1>;
368 compatible = "allwinner,sun7i-a20-mmc";
369 reg = <0x01c10000 0x1000>;
370 clocks = <&ccu CLK_AHB1_MMC1>,
372 <&ccu CLK_MMC1_OUTPUT>,
373 <&ccu CLK_MMC1_SAMPLE>;
378 resets = <&ccu RST_AHB1_MMC1>;
380 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
382 #address-cells = <1>;
387 compatible = "allwinner,sun7i-a20-mmc";
388 reg = <0x01c11000 0x1000>;
389 clocks = <&ccu CLK_AHB1_MMC2>,
391 <&ccu CLK_MMC2_OUTPUT>,
392 <&ccu CLK_MMC2_SAMPLE>;
397 resets = <&ccu RST_AHB1_MMC2>;
399 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
401 #address-cells = <1>;
406 compatible = "allwinner,sun7i-a20-mmc";
407 reg = <0x01c12000 0x1000>;
408 clocks = <&ccu CLK_AHB1_MMC3>,
410 <&ccu CLK_MMC3_OUTPUT>,
411 <&ccu CLK_MMC3_SAMPLE>;
416 resets = <&ccu RST_AHB1_MMC3>;
418 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
420 #address-cells = <1>;
425 compatible = "allwinner,sun6i-a31-hdmi";
426 reg = <0x01c16000 0x1000>;
427 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>,
430 <&ccu CLK_PLL_VIDEO0_2X>,
431 <&ccu CLK_PLL_VIDEO1_2X>;
432 clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
433 resets = <&ccu RST_AHB1_HDMI>;
435 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
436 dmas = <&dma 13>, <&dma 13>, <&dma 14>;
440 #address-cells = <1>;
444 #address-cells = <1>;
448 hdmi_in_tcon0: endpoint@0 {
450 remote-endpoint = <&tcon0_out_hdmi>;
453 hdmi_in_tcon1: endpoint@1 {
455 remote-endpoint = <&tcon1_out_hdmi>;
460 #address-cells = <1>;
467 usb_otg: usb@1c19000 {
468 compatible = "allwinner,sun6i-a31-musb";
469 reg = <0x01c19000 0x0400>;
470 clocks = <&ccu CLK_AHB1_OTG>;
471 resets = <&ccu RST_AHB1_OTG>;
472 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
473 interrupt-names = "mc";
476 extcon = <&usbphy 0>;
480 usbphy: phy@1c19400 {
481 compatible = "allwinner,sun6i-a31-usb-phy";
482 reg = <0x01c19400 0x10>,
485 reg-names = "phy_ctrl",
488 clocks = <&ccu CLK_USB_PHY0>,
491 clock-names = "usb0_phy",
494 resets = <&ccu RST_USB_PHY0>,
497 reset-names = "usb0_reset",
505 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
506 reg = <0x01c1a000 0x100>;
507 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&ccu CLK_AHB1_EHCI0>;
509 resets = <&ccu RST_AHB1_EHCI0>;
516 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
517 reg = <0x01c1a400 0x100>;
518 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
520 resets = <&ccu RST_AHB1_OHCI0>;
527 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
528 reg = <0x01c1b000 0x100>;
529 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&ccu CLK_AHB1_EHCI1>;
531 resets = <&ccu RST_AHB1_EHCI1>;
538 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
539 reg = <0x01c1b400 0x100>;
540 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
541 clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
542 resets = <&ccu RST_AHB1_OHCI1>;
549 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
550 reg = <0x01c1c400 0x100>;
551 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
553 resets = <&ccu RST_AHB1_OHCI2>;
558 compatible = "allwinner,sun6i-a31-ccu";
559 reg = <0x01c20000 0x400>;
560 clocks = <&osc24M>, <&osc32k>;
561 clock-names = "hosc", "losc";
566 pio: pinctrl@1c20800 {
567 compatible = "allwinner,sun6i-a31-pinctrl";
568 reg = <0x01c20800 0x400>;
569 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
570 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
571 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
572 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>;
574 clock-names = "apb", "hosc", "losc";
576 interrupt-controller;
577 #interrupt-cells = <3>;
580 gmac_pins_gmii_a: gmac_gmii@0 {
581 pins = "PA0", "PA1", "PA2", "PA3",
582 "PA4", "PA5", "PA6", "PA7",
583 "PA8", "PA9", "PA10", "PA11",
584 "PA12", "PA13", "PA14", "PA15",
585 "PA16", "PA17", "PA18", "PA19",
586 "PA20", "PA21", "PA22", "PA23",
587 "PA24", "PA25", "PA26", "PA27";
590 * data lines in GMII mode run at 125MHz and
591 * might need a higher signal drive strength
593 drive-strength = <30>;
596 gmac_pins_mii_a: gmac_mii@0 {
597 pins = "PA0", "PA1", "PA2", "PA3",
598 "PA8", "PA9", "PA11",
599 "PA12", "PA13", "PA14", "PA19",
600 "PA20", "PA21", "PA22", "PA23",
601 "PA24", "PA26", "PA27";
605 gmac_pins_rgmii_a: gmac_rgmii@0 {
606 pins = "PA0", "PA1", "PA2", "PA3",
607 "PA9", "PA10", "PA11",
608 "PA12", "PA13", "PA14", "PA19",
609 "PA20", "PA25", "PA26", "PA27";
612 * data lines in RGMII mode use DDR mode
613 * and need a higher signal drive strength
615 drive-strength = <40>;
618 i2c0_pins_a: i2c0@0 {
619 pins = "PH14", "PH15";
623 i2c1_pins_a: i2c1@0 {
624 pins = "PH16", "PH17";
628 i2c2_pins_a: i2c2@0 {
629 pins = "PH18", "PH19";
633 lcd0_rgb888_pins: lcd0_rgb888 {
634 pins = "PD0", "PD1", "PD2", "PD3",
635 "PD4", "PD5", "PD6", "PD7",
636 "PD8", "PD9", "PD10", "PD11",
637 "PD12", "PD13", "PD14", "PD15",
638 "PD16", "PD17", "PD18", "PD19",
639 "PD20", "PD21", "PD22", "PD23",
640 "PD24", "PD25", "PD26", "PD27";
644 mmc0_pins_a: mmc0@0 {
645 pins = "PF0", "PF1", "PF2",
648 drive-strength = <30>;
652 mmc1_pins_a: mmc1@0 {
653 pins = "PG0", "PG1", "PG2", "PG3",
656 drive-strength = <30>;
660 mmc2_pins_a: mmc2@0 {
661 pins = "PC6", "PC7", "PC8", "PC9",
664 drive-strength = <30>;
668 mmc2_8bit_emmc_pins: mmc2@1 {
669 pins = "PC6", "PC7", "PC8", "PC9",
670 "PC10", "PC11", "PC12",
671 "PC13", "PC14", "PC15",
674 drive-strength = <30>;
678 mmc3_8bit_emmc_pins: mmc3@1 {
679 pins = "PC6", "PC7", "PC8", "PC9",
680 "PC10", "PC11", "PC12",
681 "PC13", "PC14", "PC15",
684 drive-strength = <40>;
688 spdif_pins_a: spdif@0 {
693 uart0_pins_a: uart0@0 {
694 pins = "PH20", "PH21";
700 compatible = "allwinner,sun4i-a10-timer";
701 reg = <0x01c20c00 0xa0>;
702 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
703 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
704 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
705 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
706 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
710 wdt1: watchdog@1c20ca0 {
711 compatible = "allwinner,sun6i-a31-wdt";
712 reg = <0x01c20ca0 0x20>;
715 spdif: spdif@1c21000 {
716 #sound-dai-cells = <0>;
717 compatible = "allwinner,sun6i-a31-spdif";
718 reg = <0x01c21000 0x400>;
719 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
720 clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>;
721 resets = <&ccu RST_APB1_SPDIF>;
722 clock-names = "apb", "spdif";
723 dmas = <&dma 2>, <&dma 2>;
724 dma-names = "rx", "tx";
729 #sound-dai-cells = <0>;
730 compatible = "allwinner,sun6i-a31-i2s";
731 reg = <0x01c22000 0x400>;
732 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
733 clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>;
734 resets = <&ccu RST_APB1_DAUDIO0>;
735 clock-names = "apb", "mod";
736 dmas = <&dma 3>, <&dma 3>;
737 dma-names = "rx", "tx";
742 #sound-dai-cells = <0>;
743 compatible = "allwinner,sun6i-a31-i2s";
744 reg = <0x01c22400 0x400>;
745 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
746 clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>;
747 resets = <&ccu RST_APB1_DAUDIO1>;
748 clock-names = "apb", "mod";
749 dmas = <&dma 4>, <&dma 4>;
750 dma-names = "rx", "tx";
754 lradc: lradc@1c22800 {
755 compatible = "allwinner,sun4i-a10-lradc-keys";
756 reg = <0x01c22800 0x100>;
757 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
762 compatible = "allwinner,sun6i-a31-ts";
763 reg = <0x01c25000 0x100>;
764 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
765 #thermal-sensor-cells = <0>;
768 uart0: serial@1c28000 {
769 compatible = "snps,dw-apb-uart";
770 reg = <0x01c28000 0x400>;
771 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&ccu CLK_APB2_UART0>;
775 resets = <&ccu RST_APB2_UART0>;
776 dmas = <&dma 6>, <&dma 6>;
777 dma-names = "rx", "tx";
781 uart1: serial@1c28400 {
782 compatible = "snps,dw-apb-uart";
783 reg = <0x01c28400 0x400>;
784 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
787 clocks = <&ccu CLK_APB2_UART1>;
788 resets = <&ccu RST_APB2_UART1>;
789 dmas = <&dma 7>, <&dma 7>;
790 dma-names = "rx", "tx";
794 uart2: serial@1c28800 {
795 compatible = "snps,dw-apb-uart";
796 reg = <0x01c28800 0x400>;
797 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
800 clocks = <&ccu CLK_APB2_UART2>;
801 resets = <&ccu RST_APB2_UART2>;
802 dmas = <&dma 8>, <&dma 8>;
803 dma-names = "rx", "tx";
807 uart3: serial@1c28c00 {
808 compatible = "snps,dw-apb-uart";
809 reg = <0x01c28c00 0x400>;
810 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
813 clocks = <&ccu CLK_APB2_UART3>;
814 resets = <&ccu RST_APB2_UART3>;
815 dmas = <&dma 9>, <&dma 9>;
816 dma-names = "rx", "tx";
820 uart4: serial@1c29000 {
821 compatible = "snps,dw-apb-uart";
822 reg = <0x01c29000 0x400>;
823 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
826 clocks = <&ccu CLK_APB2_UART4>;
827 resets = <&ccu RST_APB2_UART4>;
828 dmas = <&dma 10>, <&dma 10>;
829 dma-names = "rx", "tx";
833 uart5: serial@1c29400 {
834 compatible = "snps,dw-apb-uart";
835 reg = <0x01c29400 0x400>;
836 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
839 clocks = <&ccu CLK_APB2_UART5>;
840 resets = <&ccu RST_APB2_UART5>;
841 dmas = <&dma 22>, <&dma 22>;
842 dma-names = "rx", "tx";
847 compatible = "allwinner,sun6i-a31-i2c";
848 reg = <0x01c2ac00 0x400>;
849 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&ccu CLK_APB2_I2C0>;
851 resets = <&ccu RST_APB2_I2C0>;
853 #address-cells = <1>;
858 compatible = "allwinner,sun6i-a31-i2c";
859 reg = <0x01c2b000 0x400>;
860 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&ccu CLK_APB2_I2C1>;
862 resets = <&ccu RST_APB2_I2C1>;
864 #address-cells = <1>;
869 compatible = "allwinner,sun6i-a31-i2c";
870 reg = <0x01c2b400 0x400>;
871 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
872 clocks = <&ccu CLK_APB2_I2C2>;
873 resets = <&ccu RST_APB2_I2C2>;
875 #address-cells = <1>;
880 compatible = "allwinner,sun6i-a31-i2c";
881 reg = <0x01c2b800 0x400>;
882 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
883 clocks = <&ccu CLK_APB2_I2C3>;
884 resets = <&ccu RST_APB2_I2C3>;
886 #address-cells = <1>;
890 gmac: ethernet@1c30000 {
891 compatible = "allwinner,sun7i-a20-gmac";
892 reg = <0x01c30000 0x1054>;
893 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
894 interrupt-names = "macirq";
895 clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
896 clock-names = "stmmaceth", "allwinner_gmac_tx";
897 resets = <&ccu RST_AHB1_EMAC>;
898 reset-names = "stmmaceth";
901 snps,force_sf_dma_mode;
903 #address-cells = <1>;
907 crypto: crypto-engine@1c15000 {
908 compatible = "allwinner,sun6i-a31-crypto",
909 "allwinner,sun4i-a10-crypto";
910 reg = <0x01c15000 0x1000>;
911 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
912 clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
913 clock-names = "ahb", "mod";
914 resets = <&ccu RST_AHB1_SS>;
918 codec: codec@1c22c00 {
919 #sound-dai-cells = <0>;
920 compatible = "allwinner,sun6i-a31-codec";
921 reg = <0x01c22c00 0x400>;
922 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
923 clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
924 clock-names = "apb", "codec";
925 resets = <&ccu RST_APB1_CODEC>;
926 dmas = <&dma 15>, <&dma 15>;
927 dma-names = "rx", "tx";
932 compatible = "allwinner,sun6i-a31-hstimer",
933 "allwinner,sun7i-a20-hstimer";
934 reg = <0x01c60000 0x1000>;
935 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
936 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
937 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
939 clocks = <&ccu CLK_AHB1_HSTIMER>;
940 resets = <&ccu RST_AHB1_HSTIMER>;
944 compatible = "allwinner,sun6i-a31-spi";
945 reg = <0x01c68000 0x1000>;
946 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
947 clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
948 clock-names = "ahb", "mod";
949 dmas = <&dma 23>, <&dma 23>;
950 dma-names = "rx", "tx";
951 resets = <&ccu RST_AHB1_SPI0>;
956 compatible = "allwinner,sun6i-a31-spi";
957 reg = <0x01c69000 0x1000>;
958 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
959 clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
960 clock-names = "ahb", "mod";
961 dmas = <&dma 24>, <&dma 24>;
962 dma-names = "rx", "tx";
963 resets = <&ccu RST_AHB1_SPI1>;
968 compatible = "allwinner,sun6i-a31-spi";
969 reg = <0x01c6a000 0x1000>;
970 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
971 clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
972 clock-names = "ahb", "mod";
973 dmas = <&dma 25>, <&dma 25>;
974 dma-names = "rx", "tx";
975 resets = <&ccu RST_AHB1_SPI2>;
980 compatible = "allwinner,sun6i-a31-spi";
981 reg = <0x01c6b000 0x1000>;
982 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
983 clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
984 clock-names = "ahb", "mod";
985 dmas = <&dma 26>, <&dma 26>;
986 dma-names = "rx", "tx";
987 resets = <&ccu RST_AHB1_SPI3>;
991 gic: interrupt-controller@1c81000 {
992 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
993 reg = <0x01c81000 0x1000>,
997 interrupt-controller;
998 #interrupt-cells = <3>;
999 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1002 fe0: display-frontend@1e00000 {
1003 compatible = "allwinner,sun6i-a31-display-frontend";
1004 reg = <0x01e00000 0x20000>;
1005 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1006 clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
1007 <&ccu CLK_DRAM_FE0>;
1008 clock-names = "ahb", "mod",
1010 resets = <&ccu RST_AHB1_FE0>;
1013 #address-cells = <1>;
1017 #address-cells = <1>;
1021 fe0_out_be0: endpoint@0 {
1023 remote-endpoint = <&be0_in_fe0>;
1026 fe0_out_be1: endpoint@1 {
1028 remote-endpoint = <&be1_in_fe0>;
1034 fe1: display-frontend@1e20000 {
1035 compatible = "allwinner,sun6i-a31-display-frontend";
1036 reg = <0x01e20000 0x20000>;
1037 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1038 clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>,
1039 <&ccu CLK_DRAM_FE1>;
1040 clock-names = "ahb", "mod",
1042 resets = <&ccu RST_AHB1_FE1>;
1045 #address-cells = <1>;
1049 #address-cells = <1>;
1053 fe1_out_be0: endpoint@0 {
1055 remote-endpoint = <&be0_in_fe1>;
1058 fe1_out_be1: endpoint@1 {
1060 remote-endpoint = <&be1_in_fe1>;
1066 be1: display-backend@1e40000 {
1067 compatible = "allwinner,sun6i-a31-display-backend";
1068 reg = <0x01e40000 0x10000>;
1069 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1070 clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>,
1071 <&ccu CLK_DRAM_BE1>;
1072 clock-names = "ahb", "mod",
1074 resets = <&ccu RST_AHB1_BE1>;
1076 assigned-clocks = <&ccu CLK_BE1>;
1077 assigned-clock-rates = <300000000>;
1080 #address-cells = <1>;
1084 #address-cells = <1>;
1088 be1_in_fe0: endpoint@0 {
1090 remote-endpoint = <&fe0_out_be1>;
1093 be1_in_fe1: endpoint@1 {
1095 remote-endpoint = <&fe1_out_be1>;
1100 #address-cells = <1>;
1104 be1_out_drc1: endpoint@1 {
1106 remote-endpoint = <&drc1_in_be1>;
1113 compatible = "allwinner,sun6i-a31-drc";
1114 reg = <0x01e50000 0x10000>;
1115 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1116 clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>,
1117 <&ccu CLK_DRAM_DRC1>;
1118 clock-names = "ahb", "mod",
1120 resets = <&ccu RST_AHB1_DRC1>;
1122 assigned-clocks = <&ccu CLK_IEP_DRC1>;
1123 assigned-clock-rates = <300000000>;
1126 #address-cells = <1>;
1130 #address-cells = <1>;
1134 drc1_in_be1: endpoint@1 {
1136 remote-endpoint = <&be1_out_drc1>;
1141 #address-cells = <1>;
1145 drc1_out_tcon0: endpoint@0 {
1147 remote-endpoint = <&tcon0_in_drc1>;
1150 drc1_out_tcon1: endpoint@1 {
1152 remote-endpoint = <&tcon1_in_drc1>;
1158 be0: display-backend@1e60000 {
1159 compatible = "allwinner,sun6i-a31-display-backend";
1160 reg = <0x01e60000 0x10000>;
1161 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1162 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
1163 <&ccu CLK_DRAM_BE0>;
1164 clock-names = "ahb", "mod",
1166 resets = <&ccu RST_AHB1_BE0>;
1168 assigned-clocks = <&ccu CLK_BE0>;
1169 assigned-clock-rates = <300000000>;
1172 #address-cells = <1>;
1176 #address-cells = <1>;
1180 be0_in_fe0: endpoint@0 {
1182 remote-endpoint = <&fe0_out_be0>;
1185 be0_in_fe1: endpoint@1 {
1187 remote-endpoint = <&fe1_out_be0>;
1192 #address-cells = <1>;
1196 be0_out_drc0: endpoint@0 {
1198 remote-endpoint = <&drc0_in_be0>;
1205 compatible = "allwinner,sun6i-a31-drc";
1206 reg = <0x01e70000 0x10000>;
1207 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1208 clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
1209 <&ccu CLK_DRAM_DRC0>;
1210 clock-names = "ahb", "mod",
1212 resets = <&ccu RST_AHB1_DRC0>;
1214 assigned-clocks = <&ccu CLK_IEP_DRC0>;
1215 assigned-clock-rates = <300000000>;
1218 #address-cells = <1>;
1222 #address-cells = <1>;
1226 drc0_in_be0: endpoint@0 {
1228 remote-endpoint = <&be0_out_drc0>;
1233 #address-cells = <1>;
1237 drc0_out_tcon0: endpoint@0 {
1239 remote-endpoint = <&tcon0_in_drc0>;
1242 drc0_out_tcon1: endpoint@1 {
1244 remote-endpoint = <&tcon1_in_drc0>;
1251 compatible = "allwinner,sun6i-a31-rtc";
1252 reg = <0x01f00000 0x54>;
1253 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1254 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1257 nmi_intc: interrupt-controller@1f00c00 {
1258 compatible = "allwinner,sun6i-a31-r-intc";
1259 interrupt-controller;
1260 #interrupt-cells = <2>;
1261 reg = <0x01f00c00 0x400>;
1262 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1266 compatible = "allwinner,sun6i-a31-prcm";
1267 reg = <0x01f01400 0x200>;
1270 compatible = "allwinner,sun6i-a31-ar100-clk";
1272 clocks = <&osc32k>, <&osc24M>,
1273 <&ccu CLK_PLL_PERIPH>,
1274 <&ccu CLK_PLL_PERIPH>;
1275 clock-output-names = "ar100";
1279 compatible = "fixed-factor-clock";
1284 clock-output-names = "ahb0";
1288 compatible = "allwinner,sun6i-a31-apb0-clk";
1291 clock-output-names = "apb0";
1294 apb0_gates: apb0_gates_clk {
1295 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
1298 clock-output-names = "apb0_pio", "apb0_ir",
1299 "apb0_timer", "apb0_p2wi",
1300 "apb0_uart", "apb0_1wire",
1306 compatible = "allwinner,sun4i-a10-mod0-clk";
1307 clocks = <&osc32k>, <&osc24M>;
1308 clock-output-names = "ir";
1311 apb0_rst: apb0_rst {
1312 compatible = "allwinner,sun6i-a31-clock-reset";
1318 compatible = "allwinner,sun6i-a31-cpuconfig";
1319 reg = <0x01f01c00 0x300>;
1323 compatible = "allwinner,sun5i-a13-ir";
1324 clocks = <&apb0_gates 1>, <&ir_clk>;
1325 clock-names = "apb", "ir";
1326 resets = <&apb0_rst 1>;
1327 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1328 reg = <0x01f02000 0x40>;
1329 status = "disabled";
1332 r_pio: pinctrl@1f02c00 {
1333 compatible = "allwinner,sun6i-a31-r-pinctrl";
1334 reg = <0x01f02c00 0x400>;
1335 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1337 clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
1338 clock-names = "apb", "hosc", "losc";
1339 resets = <&apb0_rst 0>;
1341 interrupt-controller;
1342 #interrupt-cells = <3>;
1352 pins = "PL0", "PL1";
1353 function = "s_p2wi";
1358 compatible = "allwinner,sun6i-a31-p2wi";
1359 reg = <0x01f03400 0x400>;
1360 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1361 clocks = <&apb0_gates 3>;
1362 clock-frequency = <100000>;
1363 resets = <&apb0_rst 3>;
1364 pinctrl-names = "default";
1365 pinctrl-0 = <&p2wi_pins>;
1366 status = "disabled";
1367 #address-cells = <1>;