arch/arm/dts/sun5i.dtsi

   1 /*
   2  * Copyright 2012-2015 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This library is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This library is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  *     You should have received a copy of the GNU General Public
  22  *     License along with this library; if not, write to the Free
  23  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  24  *     MA 02110-1301 USA
  25  *
  26  * Or, alternatively,
  27  *
  28  *  b) Permission is hereby granted, free of charge, to any person
  29  *     obtaining a copy of this software and associated documentation
  30  *     files (the "Software"), to deal in the Software without
  31  *     restriction, including without limitation the rights to use,
  32  *     copy, modify, merge, publish, distribute, sublicense, and/or
  33  *     sell copies of the Software, and to permit persons to whom the
  34  *     Software is furnished to do so, subject to the following
  35  *     conditions:
  36  *
  37  *     The above copyright notice and this permission notice shall be
  38  *     included in all copies or substantial portions of the Software.
  39  *
  40  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  41  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  42  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  43  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  44  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  45  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  46  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  47  *     OTHER DEALINGS IN THE SOFTWARE.
  48  */
  49
  50 #include "skeleton.dtsi"
  51
  52 #include <dt-bindings/dma/sun4i-a10.h>
  53 #include <dt-bindings/pinctrl/sun4i-a10.h>
  54
  55 / {
  56         interrupt-parent = <&intc>;
  57
  58         cpus {
  59                 #address-cells = <1>;
  60                 #size-cells = <0>;
  61
  62                 cpu0: cpu@0 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a8";
  65                         reg = <0x0>;
  66                         clocks = <&cpu>;
  67                 };
  68         };
  69
  70         clocks {
  71                 #address-cells = <1>;
  72                 #size-cells = <1>;
  73                 ranges;
  74
  75                 /*
  76                  * This is a dummy clock, to be used as placeholder on
  77                  * other mux clocks when a specific parent clock is not
  78                  * yet implemented. It should be dropped when the driver
  79                  * is complete.
  80                  */
  81                 dummy: dummy {
  82                         #clock-cells = <0>;
  83                         compatible = "fixed-clock";
  84                         clock-frequency = <0>;
  85                 };
  86
  87                 osc24M: clk@01c20050 {
  88                         #clock-cells = <0>;
  89                         compatible = "allwinner,sun4i-a10-osc-clk";
  90                         reg = <0x01c20050 0x4>;
  91                         clock-frequency = <24000000>;
  92                         clock-output-names = "osc24M";
  93                 };
  94
  95                 osc32k: clk@0 {
  96                         #clock-cells = <0>;
  97                         compatible = "fixed-clock";
  98                         clock-frequency = <32768>;
  99                         clock-output-names = "osc32k";
 100                 };
 101
 102                 pll1: clk@01c20000 {
 103                         #clock-cells = <0>;
 104                         compatible = "allwinner,sun4i-a10-pll1-clk";
 105                         reg = <0x01c20000 0x4>;
 106                         clocks = <&osc24M>;
 107                         clock-output-names = "pll1";
 108                 };
 109
 110                 pll4: clk@01c20018 {
 111                         #clock-cells = <0>;
 112                         compatible = "allwinner,sun4i-a10-pll1-clk";
 113                         reg = <0x01c20018 0x4>;
 114                         clocks = <&osc24M>;
 115                         clock-output-names = "pll4";
 116                 };
 117
 118                 pll5: clk@01c20020 {
 119                         #clock-cells = <1>;
 120                         compatible = "allwinner,sun4i-a10-pll5-clk";
 121                         reg = <0x01c20020 0x4>;
 122                         clocks = <&osc24M>;
 123                         clock-output-names = "pll5_ddr", "pll5_other";
 124                 };
 125
 126                 pll6: clk@01c20028 {
 127                         #clock-cells = <1>;
 128                         compatible = "allwinner,sun4i-a10-pll6-clk";
 129                         reg = <0x01c20028 0x4>;
 130                         clocks = <&osc24M>;
 131                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 132                 };
 133
 134                 /* dummy is 200M */
 135                 cpu: cpu@01c20054 {
 136                         #clock-cells = <0>;
 137                         compatible = "allwinner,sun4i-a10-cpu-clk";
 138                         reg = <0x01c20054 0x4>;
 139                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
 140                         clock-output-names = "cpu";
 141                 };
 142
 143                 axi: axi@01c20054 {
 144                         #clock-cells = <0>;
 145                         compatible = "allwinner,sun4i-a10-axi-clk";
 146                         reg = <0x01c20054 0x4>;
 147                         clocks = <&cpu>;
 148                         clock-output-names = "axi";
 149                 };
 150
 151                 ahb: ahb@01c20054 {
 152                         #clock-cells = <0>;
 153                         compatible = "allwinner,sun4i-a10-ahb-clk";
 154                         reg = <0x01c20054 0x4>;
 155                         clocks = <&axi>;
 156                         clock-output-names = "ahb";
 157                 };
 158
 159                 apb0: apb0@01c20054 {
 160                         #clock-cells = <0>;
 161                         compatible = "allwinner,sun4i-a10-apb0-clk";
 162                         reg = <0x01c20054 0x4>;
 163                         clocks = <&ahb>;
 164                         clock-output-names = "apb0";
 165                 };
 166
 167                 apb1: clk@01c20058 {
 168                         #clock-cells = <0>;
 169                         compatible = "allwinner,sun4i-a10-apb1-clk";
 170                         reg = <0x01c20058 0x4>;
 171                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 172                         clock-output-names = "apb1";
 173                 };
 174
 175                 axi_gates: clk@01c2005c {
 176                         #clock-cells = <1>;
 177                         compatible = "allwinner,sun4i-a10-axi-gates-clk";
 178                         reg = <0x01c2005c 0x4>;
 179                         clocks = <&axi>;
 180                         clock-output-names = "axi_dram";
 181                 };
 182
 183                 nand_clk: clk@01c20080 {
 184                         #clock-cells = <0>;
 185                         compatible = "allwinner,sun4i-a10-mod0-clk";
 186                         reg = <0x01c20080 0x4>;
 187                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 188                         clock-output-names = "nand";
 189                 };
 190
 191                 ms_clk: clk@01c20084 {
 192                         #clock-cells = <0>;
 193                         compatible = "allwinner,sun4i-a10-mod0-clk";
 194                         reg = <0x01c20084 0x4>;
 195                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 196                         clock-output-names = "ms";
 197                 };
 198
 199                 mmc0_clk: clk@01c20088 {
 200                         #clock-cells = <1>;
 201                         compatible = "allwinner,sun4i-a10-mmc-clk";
 202                         reg = <0x01c20088 0x4>;
 203                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 204                         clock-output-names = "mmc0",
 205                                              "mmc0_output",
 206                                              "mmc0_sample";
 207                 };
 208
 209                 mmc1_clk: clk@01c2008c {
 210                         #clock-cells = <1>;
 211                         compatible = "allwinner,sun4i-a10-mmc-clk";
 212                         reg = <0x01c2008c 0x4>;
 213                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 214                         clock-output-names = "mmc1",
 215                                              "mmc1_output",
 216                                              "mmc1_sample";
 217                 };
 218
 219                 mmc2_clk: clk@01c20090 {
 220                         #clock-cells = <1>;
 221                         compatible = "allwinner,sun4i-a10-mmc-clk";
 222                         reg = <0x01c20090 0x4>;
 223                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 224                         clock-output-names = "mmc2",
 225                                              "mmc2_output",
 226                                              "mmc2_sample";
 227                 };
 228
 229                 ts_clk: clk@01c20098 {
 230                         #clock-cells = <0>;
 231                         compatible = "allwinner,sun4i-a10-mod0-clk";
 232                         reg = <0x01c20098 0x4>;
 233                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 234                         clock-output-names = "ts";
 235                 };
 236
 237                 ss_clk: clk@01c2009c {
 238                         #clock-cells = <0>;
 239                         compatible = "allwinner,sun4i-a10-mod0-clk";
 240                         reg = <0x01c2009c 0x4>;
 241                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 242                         clock-output-names = "ss";
 243                 };
 244
 245                 spi0_clk: clk@01c200a0 {
 246                         #clock-cells = <0>;
 247                         compatible = "allwinner,sun4i-a10-mod0-clk";
 248                         reg = <0x01c200a0 0x4>;
 249                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 250                         clock-output-names = "spi0";
 251                 };
 252
 253                 spi1_clk: clk@01c200a4 {
 254                         #clock-cells = <0>;
 255                         compatible = "allwinner,sun4i-a10-mod0-clk";
 256                         reg = <0x01c200a4 0x4>;
 257                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 258                         clock-output-names = "spi1";
 259                 };
 260
 261                 spi2_clk: clk@01c200a8 {
 262                         #clock-cells = <0>;
 263                         compatible = "allwinner,sun4i-a10-mod0-clk";
 264                         reg = <0x01c200a8 0x4>;
 265                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 266                         clock-output-names = "spi2";
 267                 };
 268
 269                 ir0_clk: clk@01c200b0 {
 270                         #clock-cells = <0>;
 271                         compatible = "allwinner,sun4i-a10-mod0-clk";
 272                         reg = <0x01c200b0 0x4>;
 273                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 274                         clock-output-names = "ir0";
 275                 };
 276
 277                 usb_clk: clk@01c200cc {
 278                         #clock-cells = <1>;
 279                         #reset-cells = <1>;
 280                         compatible = "allwinner,sun5i-a13-usb-clk";
 281                         reg = <0x01c200cc 0x4>;
 282                         clocks = <&pll6 1>;
 283                         clock-output-names = "usb_ohci0", "usb_phy";
 284                 };
 285
 286                 mbus_clk: clk@01c2015c {
 287                         #clock-cells = <0>;
 288                         compatible = "allwinner,sun5i-a13-mbus-clk";
 289                         reg = <0x01c2015c 0x4>;
 290                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 291                         clock-output-names = "mbus";
 292                 };
 293         };
 294
 295         /*
 296          * Note we use the address where the mmio registers start, not where
 297          * the SRAM blocks start, this cannot be changed because that would be
 298          * a devicetree ABI change.
 299          */
 300         soc@01c00000 {
 301                 compatible = "simple-bus";
 302                 #address-cells = <1>;
 303                 #size-cells = <1>;
 304                 ranges;
 305
 306                 sram@00000000 {
 307                         compatible = "allwinner,sun4i-a10-sram";
 308                         reg = <0x00000000 0x4000>;
 309                         allwinner,sram-name = "A1";
 310                 };
 311
 312                 sram@00004000 {
 313                         compatible = "allwinner,sun4i-a10-sram";
 314                         reg = <0x00004000 0x4000>;
 315                         allwinner,sram-name = "A2";
 316                 };
 317
 318                 sram@00008000 {
 319                         compatible = "allwinner,sun4i-a10-sram";
 320                         reg = <0x00008000 0x4000>;
 321                         allwinner,sram-name = "A3-A4";
 322                 };
 323
 324                 sram@00010000 {
 325                         compatible = "allwinner,sun4i-a10-sram";
 326                         reg = <0x00010000 0x1000>;
 327                         allwinner,sram-name = "D";
 328                 };
 329
 330                 sram-controller@01c00000 {
 331                         compatible = "allwinner,sun4i-a10-sram-controller";
 332                         reg = <0x01c00000 0x30>;
 333                 };
 334
 335                 dma: dma-controller@01c02000 {
 336                         compatible = "allwinner,sun4i-a10-dma";
 337                         reg = <0x01c02000 0x1000>;
 338                         interrupts = <27>;
 339                         clocks = <&ahb_gates 6>;
 340                         #dma-cells = <2>;
 341                 };
 342
 343                 spi0: spi@01c05000 {
 344                         compatible = "allwinner,sun4i-a10-spi";
 345                         reg = <0x01c05000 0x1000>;
 346                         interrupts = <10>;
 347                         clocks = <&ahb_gates 20>, <&spi0_clk>;
 348                         clock-names = "ahb", "mod";
 349                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 350                                <&dma SUN4I_DMA_DEDICATED 26>;
 351                         dma-names = "rx", "tx";
 352                         status = "disabled";
 353                         #address-cells = <1>;
 354                         #size-cells = <0>;
 355                 };
 356
 357                 spi1: spi@01c06000 {
 358                         compatible = "allwinner,sun4i-a10-spi";
 359                         reg = <0x01c06000 0x1000>;
 360                         interrupts = <11>;
 361                         clocks = <&ahb_gates 21>, <&spi1_clk>;
 362                         clock-names = "ahb", "mod";
 363                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 364                                <&dma SUN4I_DMA_DEDICATED 8>;
 365                         dma-names = "rx", "tx";
 366                         status = "disabled";
 367                         #address-cells = <1>;
 368                         #size-cells = <0>;
 369                 };
 370
 371                 mmc0: mmc@01c0f000 {
 372                         compatible = "allwinner,sun5i-a13-mmc";
 373                         reg = <0x01c0f000 0x1000>;
 374                         clocks = <&ahb_gates 8>,
 375                                  <&mmc0_clk 0>,
 376                                  <&mmc0_clk 1>,
 377                                  <&mmc0_clk 2>;
 378                         clock-names = "ahb",
 379                                       "mmc",
 380                                       "output",
 381                                       "sample";
 382                         interrupts = <32>;
 383                         status = "disabled";
 384                         #address-cells = <1>;
 385                         #size-cells = <0>;
 386                 };
 387
 388                 mmc1: mmc@01c10000 {
 389                         compatible = "allwinner,sun5i-a13-mmc";
 390                         reg = <0x01c10000 0x1000>;
 391                         clocks = <&ahb_gates 9>,
 392                                  <&mmc1_clk 0>,
 393                                  <&mmc1_clk 1>,
 394                                  <&mmc1_clk 2>;
 395                         clock-names = "ahb",
 396                                       "mmc",
 397                                       "output",
 398                                       "sample";
 399                         interrupts = <33>;
 400                         status = "disabled";
 401                         #address-cells = <1>;
 402                         #size-cells = <0>;
 403                 };
 404
 405                 mmc2: mmc@01c11000 {
 406                         compatible = "allwinner,sun5i-a13-mmc";
 407                         reg = <0x01c11000 0x1000>;
 408                         clocks = <&ahb_gates 10>,
 409                                  <&mmc2_clk 0>,
 410                                  <&mmc2_clk 1>,
 411                                  <&mmc2_clk 2>;
 412                         clock-names = "ahb",
 413                                       "mmc",
 414                                       "output",
 415                                       "sample";
 416                         interrupts = <34>;
 417                         status = "disabled";
 418                         #address-cells = <1>;
 419                         #size-cells = <0>;
 420                 };
 421
 422                 usbphy: phy@01c13400 {
 423                         #phy-cells = <1>;
 424                         compatible = "allwinner,sun5i-a13-usb-phy";
 425                         reg = <0x01c13400 0x10 0x01c14800 0x4>;
 426                         reg-names = "phy_ctrl", "pmu1";
 427                         clocks = <&usb_clk 8>;
 428                         clock-names = "usb_phy";
 429                         resets = <&usb_clk 0>, <&usb_clk 1>;
 430                         reset-names = "usb0_reset", "usb1_reset";
 431                         status = "disabled";
 432                 };
 433
 434                 ehci0: usb@01c14000 {
 435                         compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
 436                         reg = <0x01c14000 0x100>;
 437                         interrupts = <39>;
 438                         clocks = <&ahb_gates 1>;
 439                         phys = <&usbphy 1>;
 440                         phy-names = "usb";
 441                         status = "disabled";
 442                 };
 443
 444                 ohci0: usb@01c14400 {
 445                         compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
 446                         reg = <0x01c14400 0x100>;
 447                         interrupts = <40>;
 448                         clocks = <&usb_clk 6>, <&ahb_gates 2>;
 449                         phys = <&usbphy 1>;
 450                         phy-names = "usb";
 451                         status = "disabled";
 452                 };
 453
 454                 spi2: spi@01c17000 {
 455                         compatible = "allwinner,sun4i-a10-spi";
 456                         reg = <0x01c17000 0x1000>;
 457                         interrupts = <12>;
 458                         clocks = <&ahb_gates 22>, <&spi2_clk>;
 459                         clock-names = "ahb", "mod";
 460                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 461                                <&dma SUN4I_DMA_DEDICATED 28>;
 462                         dma-names = "rx", "tx";
 463                         status = "disabled";
 464                         #address-cells = <1>;
 465                         #size-cells = <0>;
 466                 };
 467
 468                 intc: interrupt-controller@01c20400 {
 469                         compatible = "allwinner,sun4i-a10-ic";
 470                         reg = <0x01c20400 0x400>;
 471                         interrupt-controller;
 472                         #interrupt-cells = <1>;
 473                 };
 474
 475                 pio: pinctrl@01c20800 {
 476                         reg = <0x01c20800 0x400>;
 477                         interrupts = <28>;
 478                         clocks = <&apb0_gates 5>;
 479                         gpio-controller;
 480                         interrupt-controller;
 481                         #interrupt-cells = <2>;
 482                         #size-cells = <0>;
 483                         #gpio-cells = <3>;
 484
 485                         i2c0_pins_a: i2c0@0 {
 486                                 allwinner,pins = "PB0", "PB1";
 487                                 allwinner,function = "i2c0";
 488                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 489                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 490                         };
 491
 492                         i2c1_pins_a: i2c1@0 {
 493                                 allwinner,pins = "PB15", "PB16";
 494                                 allwinner,function = "i2c1";
 495                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 496                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 497                         };
 498
 499                         i2c2_pins_a: i2c2@0 {
 500                                 allwinner,pins = "PB17", "PB18";
 501                                 allwinner,function = "i2c2";
 502                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 503                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 504                         };
 505
 506                         mmc0_pins_a: mmc0@0 {
 507                                 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 508                                 allwinner,function = "mmc0";
 509                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 510                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 511                         };
 512
 513                         mmc2_pins_a: mmc2@0 {
 514                                 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
 515                                         "PC10", "PC11", "PC12", "PC13",
 516                                         "PC14", "PC15";
 517                                 allwinner,function = "mmc2";
 518                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 519                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 520                         };
 521                 };
 522
 523                 timer@01c20c00 {
 524                         compatible = "allwinner,sun4i-a10-timer";
 525                         reg = <0x01c20c00 0x90>;
 526                         interrupts = <22>;
 527                         clocks = <&osc24M>;
 528                 };
 529
 530                 wdt: watchdog@01c20c90 {
 531                         compatible = "allwinner,sun4i-a10-wdt";
 532                         reg = <0x01c20c90 0x10>;
 533                 };
 534
 535                 lradc: lradc@01c22800 {
 536                         compatible = "allwinner,sun4i-a10-lradc-keys";
 537                         reg = <0x01c22800 0x100>;
 538                         interrupts = <31>;
 539                         status = "disabled";
 540                 };
 541
 542                 sid: eeprom@01c23800 {
 543                         compatible = "allwinner,sun4i-a10-sid";
 544                         reg = <0x01c23800 0x10>;
 545                 };
 546
 547                 rtp: rtp@01c25000 {
 548                         compatible = "allwinner,sun5i-a13-ts";
 549                         reg = <0x01c25000 0x100>;
 550                         interrupts = <29>;
 551                         #thermal-sensor-cells = <0>;
 552                 };
 553
 554                 uart1: serial@01c28400 {
 555                         compatible = "snps,dw-apb-uart";
 556                         reg = <0x01c28400 0x400>;
 557                         interrupts = <2>;
 558                         reg-shift = <2>;
 559                         reg-io-width = <4>;
 560                         clocks = <&apb1_gates 17>;
 561                         status = "disabled";
 562                 };
 563
 564                 uart3: serial@01c28c00 {
 565                         compatible = "snps,dw-apb-uart";
 566                         reg = <0x01c28c00 0x400>;
 567                         interrupts = <4>;
 568                         reg-shift = <2>;
 569                         reg-io-width = <4>;
 570                         clocks = <&apb1_gates 19>;
 571                         status = "disabled";
 572                 };
 573
 574                 i2c0: i2c@01c2ac00 {
 575                         compatible = "allwinner,sun4i-a10-i2c";
 576                         reg = <0x01c2ac00 0x400>;
 577                         interrupts = <7>;
 578                         clocks = <&apb1_gates 0>;
 579                         status = "disabled";
 580                         #address-cells = <1>;
 581                         #size-cells = <0>;
 582                 };
 583
 584                 i2c1: i2c@01c2b000 {
 585                         compatible = "allwinner,sun4i-a10-i2c";
 586                         reg = <0x01c2b000 0x400>;
 587                         interrupts = <8>;
 588                         clocks = <&apb1_gates 1>;
 589                         status = "disabled";
 590                         #address-cells = <1>;
 591                         #size-cells = <0>;
 592                 };
 593
 594                 i2c2: i2c@01c2b400 {
 595                         compatible = "allwinner,sun4i-a10-i2c";
 596                         reg = <0x01c2b400 0x400>;
 597                         interrupts = <9>;
 598                         clocks = <&apb1_gates 2>;
 599                         status = "disabled";
 600                         #address-cells = <1>;
 601                         #size-cells = <0>;
 602                 };
 603
 604                 timer@01c60000 {
 605                         compatible = "allwinner,sun5i-a13-hstimer";
 606                         reg = <0x01c60000 0x1000>;
 607                         interrupts = <82>, <83>;
 608                         clocks = <&ahb_gates 28>;
 609                 };
 610         };
 611 };