1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
3 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/sun50i-h6-ccu.h>
8 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
9 #include <dt-bindings/clock/sun8i-de2.h>
10 #include <dt-bindings/clock/sun8i-tcon-top.h>
11 #include <dt-bindings/reset/sun50i-h6-ccu.h>
12 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
13 #include <dt-bindings/reset/sun8i-de2.h>
16 interrupt-parent = <&gic>;
25 compatible = "arm,cortex-a53";
28 enable-method = "psci";
32 compatible = "arm,cortex-a53";
35 enable-method = "psci";
39 compatible = "arm,cortex-a53";
42 enable-method = "psci";
46 compatible = "arm,cortex-a53";
49 enable-method = "psci";
54 compatible = "allwinner,sun50i-h6-display-engine";
55 allwinner,pipelines = <&mixer0>;
59 iosc: internal-osc-clk {
61 compatible = "fixed-clock";
62 clock-frequency = <16000000>;
63 clock-accuracy = <300000000>;
64 clock-output-names = "iosc";
69 compatible = "fixed-clock";
70 clock-frequency = <24000000>;
71 clock-output-names = "osc24M";
76 compatible = "fixed-clock";
77 clock-frequency = <32768>;
78 clock-output-names = "osc32k";
82 compatible = "arm,psci-0.2";
87 compatible = "arm,armv8-timer";
88 interrupts = <GIC_PPI 13
89 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
91 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
93 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
95 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
99 compatible = "simple-bus";
100 #address-cells = <1>;
104 display-engine@1000000 {
105 compatible = "allwinner,sun50i-h6-de3",
106 "allwinner,sun50i-a64-de2";
107 reg = <0x1000000 0x400000>;
108 allwinner,sram = <&de2_sram 1>;
109 #address-cells = <1>;
111 ranges = <0 0x1000000 0x400000>;
113 display_clocks: clock@0 {
114 compatible = "allwinner,sun50i-h6-de3-clk";
116 clocks = <&ccu CLK_DE>,
120 resets = <&ccu RST_BUS_DE>;
125 mixer0: mixer@100000 {
126 compatible = "allwinner,sun50i-h6-de3-mixer-0";
127 reg = <0x100000 0x100000>;
128 clocks = <&display_clocks CLK_BUS_MIXER0>,
129 <&display_clocks CLK_MIXER0>;
132 resets = <&display_clocks RST_MIXER0>;
135 #address-cells = <1>;
141 mixer0_out_tcon_top_mixer0: endpoint {
142 remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
149 video-codec@1c0e000 {
150 compatible = "allwinner,sun50i-h6-video-engine";
151 reg = <0x01c0e000 0x2000>;
152 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
154 clock-names = "ahb", "mod", "ram";
155 resets = <&ccu RST_BUS_VE>;
156 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
157 allwinner,sram = <&ve_sram 1>;
160 syscon: syscon@3000000 {
161 compatible = "allwinner,sun50i-h6-system-control",
162 "allwinner,sun50i-a64-system-control";
163 reg = <0x03000000 0x1000>;
164 #address-cells = <1>;
169 compatible = "mmio-sram";
170 reg = <0x00028000 0x1e000>;
171 #address-cells = <1>;
173 ranges = <0 0x00028000 0x1e000>;
175 de2_sram: sram-section@0 {
176 compatible = "allwinner,sun50i-h6-sram-c",
177 "allwinner,sun50i-a64-sram-c";
178 reg = <0x0000 0x1e000>;
182 sram_c1: sram@1a00000 {
183 compatible = "mmio-sram";
184 reg = <0x01a00000 0x200000>;
185 #address-cells = <1>;
187 ranges = <0 0x01a00000 0x200000>;
189 ve_sram: sram-section@0 {
190 compatible = "allwinner,sun50i-h6-sram-c1",
191 "allwinner,sun4i-a10-sram-c1";
192 reg = <0x000000 0x200000>;
198 compatible = "allwinner,sun50i-h6-ccu";
199 reg = <0x03001000 0x1000>;
200 clocks = <&osc24M>, <&osc32k>, <&iosc>;
201 clock-names = "hosc", "losc", "iosc";
207 compatible = "allwinner,sun50i-h6-sid";
208 reg = <0x03006000 0x400>;
211 pio: pinctrl@300b000 {
212 compatible = "allwinner,sun50i-h6-pinctrl";
213 reg = <0x0300b000 0x400>;
214 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>;
219 clock-names = "apb", "hosc", "losc";
222 interrupt-controller;
223 #interrupt-cells = <3>;
225 ext_rgmii_pins: rgmii-pins {
226 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
227 "PD5", "PD7", "PD8", "PD9", "PD10",
228 "PD11", "PD12", "PD13", "PD19", "PD20";
230 drive-strength = <40>;
233 hdmi_pins: hdmi-pins {
234 pins = "PH8", "PH9", "PH10";
238 mmc0_pins: mmc0-pins {
239 pins = "PF0", "PF1", "PF2", "PF3",
242 drive-strength = <30>;
246 mmc2_pins: mmc2-pins {
247 pins = "PC1", "PC4", "PC5", "PC6",
248 "PC7", "PC8", "PC9", "PC10",
249 "PC11", "PC12", "PC13", "PC14";
251 drive-strength = <30>;
255 uart0_ph_pins: uart0-ph-pins {
261 gic: interrupt-controller@3021000 {
262 compatible = "arm,gic-400";
263 reg = <0x03021000 0x1000>,
267 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
268 interrupt-controller;
269 #interrupt-cells = <3>;
273 compatible = "allwinner,sun50i-h6-mmc",
274 "allwinner,sun50i-a64-mmc";
275 reg = <0x04020000 0x1000>;
276 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
277 clock-names = "ahb", "mmc";
278 resets = <&ccu RST_BUS_MMC0>;
280 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
281 pinctrl-names = "default";
282 pinctrl-0 = <&mmc0_pins>;
284 #address-cells = <1>;
289 compatible = "allwinner,sun50i-h6-mmc",
290 "allwinner,sun50i-a64-mmc";
291 reg = <0x04021000 0x1000>;
292 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
293 clock-names = "ahb", "mmc";
294 resets = <&ccu RST_BUS_MMC1>;
296 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
298 #address-cells = <1>;
303 compatible = "allwinner,sun50i-h6-emmc",
304 "allwinner,sun50i-a64-emmc";
305 reg = <0x04022000 0x1000>;
306 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
307 clock-names = "ahb", "mmc";
308 resets = <&ccu RST_BUS_MMC2>;
310 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
311 pinctrl-names = "default";
312 pinctrl-0 = <&mmc2_pins>;
314 #address-cells = <1>;
318 uart0: serial@5000000 {
319 compatible = "snps,dw-apb-uart";
320 reg = <0x05000000 0x400>;
321 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&ccu CLK_BUS_UART0>;
325 resets = <&ccu RST_BUS_UART0>;
329 uart1: serial@5000400 {
330 compatible = "snps,dw-apb-uart";
331 reg = <0x05000400 0x400>;
332 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&ccu CLK_BUS_UART1>;
336 resets = <&ccu RST_BUS_UART1>;
340 uart2: serial@5000800 {
341 compatible = "snps,dw-apb-uart";
342 reg = <0x05000800 0x400>;
343 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&ccu CLK_BUS_UART2>;
347 resets = <&ccu RST_BUS_UART2>;
351 uart3: serial@5000c00 {
352 compatible = "snps,dw-apb-uart";
353 reg = <0x05000c00 0x400>;
354 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&ccu CLK_BUS_UART3>;
358 resets = <&ccu RST_BUS_UART3>;
362 emac: ethernet@5020000 {
363 compatible = "allwinner,sun50i-h6-emac",
364 "allwinner,sun50i-a64-emac";
366 reg = <0x05020000 0x10000>;
367 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
368 interrupt-names = "macirq";
369 resets = <&ccu RST_BUS_EMAC>;
370 reset-names = "stmmaceth";
371 clocks = <&ccu CLK_BUS_EMAC>;
372 clock-names = "stmmaceth";
376 compatible = "snps,dwmac-mdio";
377 #address-cells = <1>;
382 usb2otg: usb@5100000 {
383 compatible = "allwinner,sun50i-h6-musb",
384 "allwinner,sun8i-a33-musb";
385 reg = <0x05100000 0x0400>;
386 clocks = <&ccu CLK_BUS_OTG>;
387 resets = <&ccu RST_BUS_OTG>;
388 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
389 interrupt-names = "mc";
392 extcon = <&usb2phy 0>;
396 usb2phy: phy@5100400 {
397 compatible = "allwinner,sun50i-h6-usb-phy";
398 reg = <0x05100400 0x24>,
401 reg-names = "phy_ctrl",
404 clocks = <&ccu CLK_USB_PHY0>,
406 clock-names = "usb0_phy",
408 resets = <&ccu RST_USB_PHY0>,
410 reset-names = "usb0_reset",
417 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
418 reg = <0x05101000 0x100>;
419 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&ccu CLK_BUS_OHCI0>,
421 <&ccu CLK_BUS_EHCI0>,
422 <&ccu CLK_USB_OHCI0>;
423 resets = <&ccu RST_BUS_OHCI0>,
424 <&ccu RST_BUS_EHCI0>;
429 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
430 reg = <0x05101400 0x100>;
431 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&ccu CLK_BUS_OHCI0>,
433 <&ccu CLK_USB_OHCI0>;
434 resets = <&ccu RST_BUS_OHCI0>;
439 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
440 reg = <0x05311000 0x100>;
441 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&ccu CLK_BUS_OHCI3>,
443 <&ccu CLK_BUS_EHCI3>,
444 <&ccu CLK_USB_OHCI3>;
445 resets = <&ccu RST_BUS_OHCI3>,
446 <&ccu RST_BUS_EHCI3>;
453 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
454 reg = <0x05311400 0x100>;
455 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&ccu CLK_BUS_OHCI3>,
457 <&ccu CLK_USB_OHCI3>;
458 resets = <&ccu RST_BUS_OHCI3>;
465 compatible = "allwinner,sun50i-h6-dw-hdmi";
466 reg = <0x06000000 0x10000>;
468 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
470 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
471 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
472 clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
474 resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
475 reset-names = "ctrl", "hdcp";
477 phy-names = "hdmi-phy";
478 pinctrl-names = "default";
479 pinctrl-0 = <&hdmi_pins>;
483 #address-cells = <1>;
489 hdmi_in_tcon_top: endpoint {
490 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
500 hdmi_phy: hdmi-phy@6010000 {
501 compatible = "allwinner,sun50i-h6-hdmi-phy";
502 reg = <0x06010000 0x10000>;
503 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
504 clock-names = "bus", "mod";
505 resets = <&ccu RST_BUS_HDMI>;
510 tcon_top: tcon-top@6510000 {
511 compatible = "allwinner,sun50i-h6-tcon-top";
512 reg = <0x06510000 0x1000>;
513 clocks = <&ccu CLK_BUS_TCON_TOP>,
517 clock-output-names = "tcon-top-tv0";
518 resets = <&ccu RST_BUS_TCON_TOP>;
523 #address-cells = <1>;
526 tcon_top_mixer0_in: port@0 {
527 #address-cells = <1>;
531 tcon_top_mixer0_in_mixer0: endpoint@0 {
533 remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
537 tcon_top_mixer0_out: port@1 {
538 #address-cells = <1>;
542 tcon_top_mixer0_out_tcon_tv: endpoint@2 {
544 remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
548 tcon_top_hdmi_in: port@4 {
549 #address-cells = <1>;
553 tcon_top_hdmi_in_tcon_tv: endpoint@0 {
555 remote-endpoint = <&tcon_tv_out_tcon_top>;
559 tcon_top_hdmi_out: port@5 {
562 tcon_top_hdmi_out_hdmi: endpoint {
563 remote-endpoint = <&hdmi_in_tcon_top>;
569 tcon_tv: lcd-controller@6515000 {
570 compatible = "allwinner,sun50i-h6-tcon-tv",
571 "allwinner,sun8i-r40-tcon-tv";
572 reg = <0x06515000 0x1000>;
573 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&ccu CLK_BUS_TCON_TV0>,
575 <&tcon_top CLK_TCON_TOP_TV0>;
578 resets = <&ccu RST_BUS_TCON_TV0>;
582 #address-cells = <1>;
588 tcon_tv_in_tcon_top_mixer0: endpoint {
589 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
593 tcon_tv_out: port@1 {
594 #address-cells = <1>;
598 tcon_tv_out_tcon_top: endpoint@1 {
600 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
606 r_ccu: clock@7010000 {
607 compatible = "allwinner,sun50i-h6-r-ccu";
608 reg = <0x07010000 0x400>;
609 clocks = <&osc24M>, <&osc32k>, <&iosc>,
610 <&ccu CLK_PLL_PERIPH0>;
611 clock-names = "hosc", "losc", "iosc", "pll-periph";
616 r_intc: interrupt-controller@7021000 {
617 compatible = "allwinner,sun50i-h6-r-intc",
618 "allwinner,sun6i-a31-r-intc";
619 interrupt-controller;
620 #interrupt-cells = <2>;
621 reg = <0x07021000 0x400>;
622 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
625 r_pio: pinctrl@7022000 {
626 compatible = "allwinner,sun50i-h6-r-pinctrl";
627 reg = <0x07022000 0x400>;
628 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>;
631 clock-names = "apb", "hosc", "losc";
634 interrupt-controller;
635 #interrupt-cells = <3>;
637 r_i2c_pins: r-i2c-pins {
644 compatible = "allwinner,sun6i-a31-i2c";
645 reg = <0x07081400 0x400>;
646 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&r_ccu CLK_R_APB2_I2C>;
648 resets = <&r_ccu RST_R_APB2_I2C>;
649 pinctrl-names = "default";
650 pinctrl-0 = <&r_i2c_pins>;
652 #address-cells = <1>;