arm: mvebu: add nand pins
[oweals/u-boot.git] / arch / arm / dts / sun50i-a64.dtsi
1 /*
2  * Copyright (C) 2016 ARM Ltd.
3  * based on the Allwinner H3 dtsi:
4  *    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
5  *
6  * This file is dual-licensed: you can use it either under the terms
7  * of the GPL or the X11 license, at your option. Note that this dual
8  * licensing only applies to this file, and not this project as a
9  * whole.
10  *
11  *  a) This file is free software; you can redistribute it and/or
12  *     modify it under the terms of the GNU General Public License as
13  *     published by the Free Software Foundation; either version 2 of the
14  *     License, or (at your option) any later version.
15  *
16  *     This file is distributed in the hope that it will be useful,
17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19  *     GNU General Public License for more details.
20  *
21  * Or, alternatively,
22  *
23  *  b) Permission is hereby granted, free of charge, to any person
24  *     obtaining a copy of this software and associated documentation
25  *     files (the "Software"), to deal in the Software without
26  *     restriction, including without limitation the rights to use,
27  *     copy, modify, merge, publish, distribute, sublicense, and/or
28  *     sell copies of the Software, and to permit persons to whom the
29  *     Software is furnished to do so, subject to the following
30  *     conditions:
31  *
32  *     The above copyright notice and this permission notice shall be
33  *     included in all copies or substantial portions of the Software.
34  *
35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42  *     OTHER DEALINGS IN THE SOFTWARE.
43  */
44
45 #include <dt-bindings/clock/sun50i-a64-ccu.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/reset/sun50i-a64-ccu.h>
48
49 / {
50         interrupt-parent = <&gic>;
51         #address-cells = <1>;
52         #size-cells = <1>;
53
54         cpus {
55                 #address-cells = <1>;
56                 #size-cells = <0>;
57
58                 cpu0: cpu@0 {
59                         compatible = "arm,cortex-a53", "arm,armv8";
60                         device_type = "cpu";
61                         reg = <0>;
62                         enable-method = "psci";
63                 };
64
65                 cpu1: cpu@1 {
66                         compatible = "arm,cortex-a53", "arm,armv8";
67                         device_type = "cpu";
68                         reg = <1>;
69                         enable-method = "psci";
70                 };
71
72                 cpu2: cpu@2 {
73                         compatible = "arm,cortex-a53", "arm,armv8";
74                         device_type = "cpu";
75                         reg = <2>;
76                         enable-method = "psci";
77                 };
78
79                 cpu3: cpu@3 {
80                         compatible = "arm,cortex-a53", "arm,armv8";
81                         device_type = "cpu";
82                         reg = <3>;
83                         enable-method = "psci";
84                 };
85         };
86
87         osc24M: osc24M_clk {
88                 #clock-cells = <0>;
89                 compatible = "fixed-clock";
90                 clock-frequency = <24000000>;
91                 clock-output-names = "osc24M";
92         };
93
94         osc32k: osc32k_clk {
95                 #clock-cells = <0>;
96                 compatible = "fixed-clock";
97                 clock-frequency = <32768>;
98                 clock-output-names = "osc32k";
99         };
100
101         iosc: internal-osc-clk {
102                 #clock-cells = <0>;
103                 compatible = "fixed-clock";
104                 clock-frequency = <16000000>;
105                 clock-accuracy = <300000000>;
106                 clock-output-names = "iosc";
107         };
108
109         psci {
110                 compatible = "arm,psci-0.2";
111                 method = "smc";
112         };
113
114         timer {
115                 compatible = "arm,armv8-timer";
116                 interrupts = <GIC_PPI 13
117                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
118                              <GIC_PPI 14
119                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
120                              <GIC_PPI 11
121                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
122                              <GIC_PPI 10
123                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
124         };
125
126         soc {
127                 compatible = "simple-bus";
128                 #address-cells = <1>;
129                 #size-cells = <1>;
130                 ranges;
131
132                 mmc0: mmc@1c0f000 {
133                         compatible = "allwinner,sun50i-a64-mmc";
134                         reg = <0x01c0f000 0x1000>;
135                         clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
136                         clock-names = "ahb", "mmc";
137                         resets = <&ccu RST_BUS_MMC0>;
138                         reset-names = "ahb";
139                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
140                         max-frequency = <150000000>;
141                         status = "disabled";
142                         #address-cells = <1>;
143                         #size-cells = <0>;
144                 };
145
146                 mmc1: mmc@1c10000 {
147                         compatible = "allwinner,sun50i-a64-mmc";
148                         reg = <0x01c10000 0x1000>;
149                         clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
150                         clock-names = "ahb", "mmc";
151                         resets = <&ccu RST_BUS_MMC1>;
152                         reset-names = "ahb";
153                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
154                         max-frequency = <150000000>;
155                         status = "disabled";
156                         #address-cells = <1>;
157                         #size-cells = <0>;
158                 };
159
160                 mmc2: mmc@1c11000 {
161                         compatible = "allwinner,sun50i-a64-emmc";
162                         reg = <0x01c11000 0x1000>;
163                         clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
164                         clock-names = "ahb", "mmc";
165                         resets = <&ccu RST_BUS_MMC2>;
166                         reset-names = "ahb";
167                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
168                         max-frequency = <200000000>;
169                         status = "disabled";
170                         #address-cells = <1>;
171                         #size-cells = <0>;
172                 };
173
174                 usb_otg: usb@01c19000 {
175                         compatible = "allwinner,sun8i-a33-musb";
176                         reg = <0x01c19000 0x0400>;
177                         clocks = <&ccu CLK_BUS_OTG>;
178                         resets = <&ccu RST_BUS_OTG>;
179                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
180                         interrupt-names = "mc";
181                         phys = <&usbphy 0>;
182                         phy-names = "usb";
183                         extcon = <&usbphy 0>;
184                         status = "disabled";
185                 };
186
187                 usbphy: phy@01c19400 {
188                         compatible = "allwinner,sun50i-a64-usb-phy";
189                         reg = <0x01c19400 0x14>,
190                               <0x01c1a800 0x4>,
191                               <0x01c1b800 0x4>;
192                         reg-names = "phy_ctrl",
193                                     "pmu0",
194                                     "pmu1";
195                         clocks = <&ccu CLK_USB_PHY0>,
196                                  <&ccu CLK_USB_PHY1>;
197                         clock-names = "usb0_phy",
198                                       "usb1_phy";
199                         resets = <&ccu RST_USB_PHY0>,
200                                  <&ccu RST_USB_PHY1>;
201                         reset-names = "usb0_reset",
202                                       "usb1_reset";
203                         status = "disabled";
204                         #phy-cells = <1>;
205                 };
206
207                 ehci0: usb@01c1a000 {
208                         compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
209                         reg = <0x01c1a000 0x100>;
210                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
211                         clocks = <&ccu CLK_BUS_OHCI0>,
212                                  <&ccu CLK_BUS_EHCI0>,
213                                  <&ccu CLK_USB_OHCI0>;
214                         resets = <&ccu RST_BUS_OHCI0>,
215                                  <&ccu RST_BUS_EHCI0>;
216                         status = "disabled";
217                 };
218
219                 ohci0: usb@01c1a400 {
220                         compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
221                         reg = <0x01c1a400 0x100>;
222                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
223                         clocks = <&ccu CLK_BUS_OHCI0>,
224                                  <&ccu CLK_USB_OHCI0>;
225                         resets = <&ccu RST_BUS_OHCI0>;
226                         status = "disabled";
227                 };
228
229                 ehci1: usb@01c1b000 {
230                         compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
231                         reg = <0x01c1b000 0x100>;
232                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
233                         clocks = <&ccu CLK_BUS_OHCI1>,
234                                  <&ccu CLK_BUS_EHCI1>,
235                                  <&ccu CLK_USB_OHCI1>;
236                         resets = <&ccu RST_BUS_OHCI1>,
237                                  <&ccu RST_BUS_EHCI1>;
238                         phys = <&usbphy 1>;
239                         phy-names = "usb";
240                         status = "disabled";
241                 };
242
243                 ohci1: usb@01c1b400 {
244                         compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
245                         reg = <0x01c1b400 0x100>;
246                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
247                         clocks = <&ccu CLK_BUS_OHCI1>,
248                                  <&ccu CLK_USB_OHCI1>;
249                         resets = <&ccu RST_BUS_OHCI1>;
250                         phys = <&usbphy 1>;
251                         phy-names = "usb";
252                         status = "disabled";
253                 };
254
255                 ccu: clock@01c20000 {
256                         compatible = "allwinner,sun50i-a64-ccu";
257                         reg = <0x01c20000 0x400>;
258                         clocks = <&osc24M>, <&osc32k>;
259                         clock-names = "hosc", "losc";
260                         #clock-cells = <1>;
261                         #reset-cells = <1>;
262                 };
263
264                 pio: pinctrl@1c20800 {
265                         compatible = "allwinner,sun50i-a64-pinctrl";
266                         reg = <0x01c20800 0x400>;
267                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
268                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
269                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
270                         clocks = <&ccu 58>;
271                         gpio-controller;
272                         #gpio-cells = <3>;
273                         interrupt-controller;
274                         #interrupt-cells = <3>;
275
276                         i2c1_pins: i2c1_pins {
277                                 pins = "PH2", "PH3";
278                                 function = "i2c1";
279                         };
280
281                         mmc0_pins: mmc0-pins {
282                                 pins = "PF0", "PF1", "PF2", "PF3",
283                                        "PF4", "PF5";
284                                 function = "mmc0";
285                                 drive-strength = <30>;
286                                 bias-pull-up;
287                         };
288
289                         mmc1_pins: mmc1-pins {
290                                 pins = "PG0", "PG1", "PG2", "PG3",
291                                        "PG4", "PG5";
292                                 function = "mmc1";
293                                 drive-strength = <30>;
294                                 bias-pull-up;
295                         };
296
297                         mmc2_pins: mmc2-pins {
298                                 pins = "PC1", "PC5", "PC6", "PC8", "PC9",
299                                        "PC10","PC11", "PC12", "PC13",
300                                        "PC14", "PC15", "PC16";
301                                 function = "mmc2";
302                                 drive-strength = <30>;
303                                 bias-pull-up;
304                         };
305
306                         uart0_pins_a: uart0@0 {
307                                 pins = "PB8", "PB9";
308                                 function = "uart0";
309                         };
310
311                         uart1_pins: uart1_pins {
312                                 pins = "PG6", "PG7";
313                                 function = "uart1";
314                         };
315
316                         uart1_rts_cts_pins: uart1_rts_cts_pins {
317                                 pins = "PG8", "PG9";
318                                 function = "uart1";
319                         };
320                 };
321
322                 uart0: serial@1c28000 {
323                         compatible = "snps,dw-apb-uart";
324                         reg = <0x01c28000 0x400>;
325                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
326                         reg-shift = <2>;
327                         reg-io-width = <4>;
328                         clocks = <&ccu 67>;
329                         resets = <&ccu 46>;
330                         status = "disabled";
331                 };
332
333                 uart1: serial@1c28400 {
334                         compatible = "snps,dw-apb-uart";
335                         reg = <0x01c28400 0x400>;
336                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
337                         reg-shift = <2>;
338                         reg-io-width = <4>;
339                         clocks = <&ccu 68>;
340                         resets = <&ccu 47>;
341                         status = "disabled";
342                 };
343
344                 uart2: serial@1c28800 {
345                         compatible = "snps,dw-apb-uart";
346                         reg = <0x01c28800 0x400>;
347                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
348                         reg-shift = <2>;
349                         reg-io-width = <4>;
350                         clocks = <&ccu 69>;
351                         resets = <&ccu 48>;
352                         status = "disabled";
353                 };
354
355                 uart3: serial@1c28c00 {
356                         compatible = "snps,dw-apb-uart";
357                         reg = <0x01c28c00 0x400>;
358                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
359                         reg-shift = <2>;
360                         reg-io-width = <4>;
361                         clocks = <&ccu 70>;
362                         resets = <&ccu 49>;
363                         status = "disabled";
364                 };
365
366                 uart4: serial@1c29000 {
367                         compatible = "snps,dw-apb-uart";
368                         reg = <0x01c29000 0x400>;
369                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
370                         reg-shift = <2>;
371                         reg-io-width = <4>;
372                         clocks = <&ccu 71>;
373                         resets = <&ccu 50>;
374                         status = "disabled";
375                 };
376
377                 i2c0: i2c@1c2ac00 {
378                         compatible = "allwinner,sun6i-a31-i2c";
379                         reg = <0x01c2ac00 0x400>;
380                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
381                         clocks = <&ccu 63>;
382                         resets = <&ccu 42>;
383                         status = "disabled";
384                         #address-cells = <1>;
385                         #size-cells = <0>;
386                 };
387
388                 i2c1: i2c@1c2b000 {
389                         compatible = "allwinner,sun6i-a31-i2c";
390                         reg = <0x01c2b000 0x400>;
391                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
392                         clocks = <&ccu 64>;
393                         resets = <&ccu 43>;
394                         status = "disabled";
395                         #address-cells = <1>;
396                         #size-cells = <0>;
397                 };
398
399                 i2c2: i2c@1c2b400 {
400                         compatible = "allwinner,sun6i-a31-i2c";
401                         reg = <0x01c2b400 0x400>;
402                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
403                         clocks = <&ccu 65>;
404                         resets = <&ccu 44>;
405                         status = "disabled";
406                         #address-cells = <1>;
407                         #size-cells = <0>;
408                 };
409
410                 gic: interrupt-controller@1c81000 {
411                         compatible = "arm,gic-400";
412                         reg = <0x01c81000 0x1000>,
413                               <0x01c82000 0x2000>,
414                               <0x01c84000 0x2000>,
415                               <0x01c86000 0x2000>;
416                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
417                         interrupt-controller;
418                         #interrupt-cells = <3>;
419                 };
420
421                 rtc: rtc@1f00000 {
422                         compatible = "allwinner,sun6i-a31-rtc";
423                         reg = <0x01f00000 0x54>;
424                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
425                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
426                 };
427
428                 r_ccu: clock@1f01400 {
429                         compatible = "allwinner,sun50i-a64-r-ccu";
430                         reg = <0x01f01400 0x100>;
431                         clocks = <&osc24M>, <&osc32k>, <&iosc>;
432                         clock-names = "hosc", "losc", "iosc";
433                         #clock-cells = <1>;
434                         #reset-cells = <1>;
435                 };
436
437                 r_pio: pinctrl@01f02c00 {
438                         compatible = "allwinner,sun50i-a64-r-pinctrl";
439                         reg = <0x01f02c00 0x400>;
440                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
441                         clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>;
442                         clock-names = "apb", "hosc", "losc";
443                         gpio-controller;
444                         #gpio-cells = <3>;
445                         interrupt-controller;
446                         #interrupt-cells = <3>;
447                 };
448         };
449 };